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Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International

Date 17-21 Oct. 2010

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Displaying Results 1 - 25 of 55
  • [Front and back cover]

    Page(s): c1 - c4
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    Freely Available from IEEE
  • [Title page]

    Page(s): i
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    Freely Available from IEEE
  • Contents

    Page(s): iii - vi
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    Freely Available from IEEE
  • Management Committee

    Page(s): ii
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    Freely Available from IEEE
  • Foreword

    Page(s): vii
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    Freely Available from IEEE
  • Life beyond Si: More Moore or More than Moore?

    Page(s): ix
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    As the semiconductor industry accelerates on a collision course with physical and electrical roadblocks on the scaling roadmap, non-Si materials and non-traditional devices are increasingly being considered for heterogeneous integration on silicon CMOS platforms. High-k metal gates and Ge/III–V high mobility channels are some examples of materials under consideration. In addition, strong interest in low power technologies, coupled with need for increased functional diversity at the chip and system level, has lead to the investigation of devices such as MEMS integrated with CMOS and tunneling FET devices. These trends raise critical process and integration challenges, not only in making dissimilar - sometimes outright incompatible - materials and devices work seamlessly, but also in the characterization and reliability assessment. Industry trends, potential solutions around road blocks, outlook for Moore's law driven scaling vs. More than Moore options, opportunities, and gaps were discussed. View full abstract»

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  • On the universality of negative bias temperature degradation

    Page(s): 1
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    Over last five years, many industrial/academic research groups have characterized the NBTI degradation through power-law exponents, universality of relaxation, frequency and duty cycle dependencies by using a wide variety of characterization techniques. The scatter in the data has inspired a range of modeling efforts regarding NBTI degradation, with important implications for projected lifetime and technology qualification. In this talk, we will show that the scatter in the data hides a simple universality of the degradation characteristics and that universality of data imposes strict consistency requirements for NBTI theories. We conclude by showing that the existing protocol for qualification and circuit design are theoretically sound, and can be used without significant revision/refinement. View full abstract»

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  • On the ‘permanent’ component of NBTI

    Page(s): 2 - 7
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    A number of recent publications explain NBTI to be due to a recoverable and a more permanent component. While a lot of information has been gathered on the recoverable component, the permanent component has been somewhat elusive. We demonstrate that oxide defects commonly linked to the recoverable component also form an important contribution to the permanent component of NBTI. As such, they can contribute to both the threshold voltage shift as well as the charge pumping current. Under favorable conditions, the permanent component can show recovery rates comparable to that of the recoverable component. View full abstract»

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  • Recovery of negative and positive bias temperature stress in pMOSFETs

    Page(s): 8 - 11
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    Based on the asymmetric recovery behavior observed following negative and positive bias temperature stress in pMOSFETs, various stress tests with different stress times, oxide electric fields, and oxide thicknesses were performed. In contrast to NBTI, where the relaxation of the threshold voltage often follows a logarithmic behavior, PBTI stress reveals no logarithmic recovery. Notable relaxation after PBTI stress instead appears to happen later but faster. This asymmetry is more pronounced at harsher stress conditions, e.g. increasing stress time and oxide electric field. This can be explained by the different relative measurement windows for NBTI and PBTI, which depend on the stress time and the oxide electric field. A closer analysis of the recovery yields the spectra of capture and emission time constants of the underlying defects. We analyze the dependence of these spectra on the stress time and the oxide electric field, where the emission times of the defects are shifted towards smaller times for higher oxide electric field. View full abstract»

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  • The impact of recovery on BTI reliability assessments

    Page(s): 12 - 16
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    BTI is shown to be the most important device degradation mechanism for combinational logic. Significant benefits regarding lifetime predictions and the total effort in measurement time can be expected from measurements minimizing recovery by a short measuring delay or/and assessments being done with AC stress for applications ensuring AC operation only. View full abstract»

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  • Correlation between dielectric traps and BTI characteristics of high-k/ metal gate MOSFETs

    Page(s): 17 - 21
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    The extended flicker noise measurement incorporating with BTI evaluation is applied to investigate the bulk trapping density Nt in HK/MG stacks and the correlated BTI behaviors. An effective evaluating technique on BTI/TDDB is developed. This method will help to understand the physical original of BTI degradation. View full abstract»

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  • Requirement of effective fabless/foundry interactions for achieving robust product reliability

    Page(s): 22
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    It is no longer sufficient for foundries to provide only process technology qualification data (for example, device hot carrier, TDDB, BTI, interconnect EM, SM etc.) to the fabless companies as it has been done traditionally. At the nanometer scale, process variations (die to die & within die) coupled with shrinking reliability margins have significantly reduced the design space while circuit designs become increasingly complicated. Foundries need to provide detailed reliability information to enable process-variability & reliability-aware designs that allow the fabless users to leverage the benefits of the advanced technologies. The information is needed for all users and is critical to be available in the process development phase for early technology adaptors. Information should include detailed reliability design rules/tools in form of device/interconnect degradation models that incorporate statistical/process variations. These models/tools can help designers to identify and to mitigate circuit reliability risks in the early design phase. This paper addresses this shift of paradigm that allows fabless designs to keep pace with the rapidly changing nano scale technologies. View full abstract»

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  • Foundry reliability engineering requirement & challenges

    Page(s): 23
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    Summary form only given. Foundries enable a low risk, cost effective and competitive entry into the marketplace for fabless design companies. As the complexity of the technology increases due to rapid introduction of new materials, the landscape and roles of foundry reliability engineering has changed too. These changes have brought about different requirements and challenges. Foundry will be an important contributor to overcoming these challenges in collaboration with the industry leaders. View full abstract»

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  • Photovoltaic module reliability: Enduring a storm

    Page(s): 24
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    Summary form only given. In contrast to integrated circuits, solar panels need to withstand large variations in environment and weather conditions. Photovoltaic modules must withstand 0-100% humidity at -20°C to 100°C with voltages up to 1000 V and thousands of thermal cycles. Therefore, predicting lifetime is no better than predicting the weather. Yet lifetime estimates directly impact the levelized cost of a power generation system and therefore must be quantified. This talk will outline many of the failure modes for solar panels and the failure analysis techniques that are commonly used. Thermal and emission images are the dominate method for identifying egradation in a solar module. View full abstract»

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  • Soft errors — Past history and recent discoveries

    Page(s): 25 - 30
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    Soft errors from alpha particles and terrestrial neutrons have been an issue in commercial electronic systems for over three decades. Measurement and mitigation techniques are well developed, but recent work highlights new issues that will need to be addressed for deep sub-micrometer technologies. The contribution of thermal neutrons does not appear to be eliminated with BPSG-free processing. In addition, neutrons in the spectral range of 1-10 MeV appear to be significant for soft error rates. Charge sharing and multi-node effects will negate some of the redundant circuit designs. As low power devices gain in applications, the impact of soft errors in the sub-threshold region of operation will be important. View full abstract»

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  • B10 finding and correlation to thermal neutron soft error rate sensitivity for SRAMs in the sub-micron technology

    Page(s): 31 - 33
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    In this paper, we report the presence of B10 based on SIMS analysis in SRAM arrays in the 90nm to 45nm technology nodes. The physical presence of B10 correlated very well with the thermal neutron soft error rate (SER) sensitivity of SRAM cells. This result confirmed that without BPSG layer in advanced Si technologies, there is still a high possibility of B10 contamination from the Fab process. Furthermore, a root cause of possible B10 source is suggested based on SIMS results. View full abstract»

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  • Alpha emission of fully processed silicon wafers

    Page(s): 34 - 36
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    Measured alpha particle emissions from packaging materials have been used to calculate the Soft Error Rate of silicon components. The packaging materials have been assumed to be the only alpha emitter and the layers on top of the silicon have been assumed to be the alpha attenuators. This paper measures the alpha emission of the fully processed wafers from different vendors and shows that these wafers are significant alpha emitters. Because the alpha emitters in this case are very close to the silicon, there are no shielding layers to attenuate the lower energy alpha particle. The entire alpha particle energy spectrum, from both package materials to the inside wafers, must be considered, when calculating the alpha flux at the silicon die. View full abstract»

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  • Defects in low-κ dielectrics and etch stop layers for use as interlayer dielectrics in ULSI

    Page(s): 37 - 41
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    The electronic properties of thin film low-κ interlayer dielectric (ILD) and etch stop layers (ESL) are important issues in present day ULSI development.1-6 Low-κ ILD and ESLs with dielectric constants significantly less then those of SiO2 and SiN are utilized to reduce capacitance induced RC delays in ULSI circuits. However as the semiconductor industry looks to transition to 16 nm and beyond technology nodes, numerous reliability concerns with low-k materials need to be addressed. In particular, leakage currents, time dependent dielectric breakdown (TDDM) and stress induced leakage currents (SILC) are critical problems that are not yet well understood in ILD. A topic of current interest is ultraviolet light (UV curing) of low-k materials.5,6 We have made electron spin resonance (ESR) and current density versus voltage measurements on a moderately extensive set of dielectric/silicon structures involving materials of importance to low-k interconnect systems. Most of the dielectrics studied involve various compositions of SiOC:H. In addition we have also made measurements on other dielectrics including SiO2, SiCN:H and SiN:H. View full abstract»

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  • Copper - top interconnect reliability for mixed signal applications

    Page(s): 42 - 45
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    The equation of resistance drift governing oxidation is derived in this paper for Copper-Top (Cu-Top) interconnects to assess reliability of Cu-Top. Our equation is not only demonstrated by thermal storage tests at various temperatures but also characterized by dependence of time, temperature, metal width, and additional dielectric & conductive layers over Cu-Top. As a result, this approach enables the prediction of the accumulated resistance drift under any conditions for a lifetime operation. View full abstract»

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  • Effect of reservoir on electromigration of short interconnects

    Page(s): 46 - 50
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    As the interconnect cross-sections are ever scaled down, a particular care must be taken on the tradeoff between increase of current density in the back end of line and reliability to prevent electromigration (EM). Some lever exists as the well-known Blech effect. One can take advantage of the EM induced backflow flux that counters the EM flux. As a consequence, the total net flux in the line is reduced and additional current density in designs can be allowed in short lines. However, the immortality condition is most of the time addressed with a standard test structures ended by two vias. Designs present complex configurations far from this typical case and the Blech product (jL)c can be deteriorated or enhanced. In the present paper, we present our study of EM performances of short lines ended by an inactive end of line (EOL) at one end of the test structure. Significant differences on the median time to failure (MTF) are observed with respect to the current direction, from a quasi deletion of failure to a significant reduction of the Blech effect. Based on the resistance saturation, a method is proposed to determine effective lengths of inactive EOL configurations corresponding to the standard case. View full abstract»

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  • Investigation into the effect of a “through silicon via”-process on the MOS transistor reliability of a standard 0.13µm CMOS technology

    Page(s): 51 - 55
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    Introducing a through-silicon-via (TSV) process into an existing technology node additional degradation mechanisms can be expected. The focus of the investigation was on mechanical stress from the TSV on near by MOS devices and plasma charging effects from the processing of the TSV connected to MOS devices. The significance of these additional effects on the MOS transistor reliability is assessed. It is shown that a TSV-process can introduce severe reliability degradation for MOS transistors. View full abstract»

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  • Impact of body tie and Source/Drain contact spacing on the hot carrier reliability of 45-nm RF-CMOS

    Page(s): 56 - 60
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    We report the hot carrier reliability (HCR) of 45-nm SOI CMOS technology. Body contacted devices are shown to be more reliable than floating-body devices. Two different body-contacting schemes are investigated (T-body and notched T- body). The effects of total dose irradiation on reliability are investigated. Body contacted devices are shown to be more tolerant to radiation than floating-body devices. Asymmetric halo doping devices show less hot carrier degradation than symmetric halo doping devices. In addition, we investigate the dependence of hot carrier reliability on the metal contact spacing of the Source/Drain (S/D) terminals, the PC-PC spacing, and the RF device performance trade-offs that result. View full abstract»

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  • Multiple microscopic defects characterization methods to improve macroscopic degradation modeling of MOSFETs

    Page(s): 61 - 66
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    Degradation modeling is based usually on macroscopic parameters which can yield to wrong conclusions, since similar degradation might result from very different microscopic situations. The focus on degradation modeling at a microscopic level is proposed. Other authors only compare results from different characterization methods on their common measurement area. This paper proposes to use their complementarities to extend the probed areas. A more accurate determination of defects is obtained with multiple characterization method cross-fertilization allowing 1) ascertaining defect localizations, 2) extending probed areas and 3) identifying microscopic differences between similar macroscopic parameters. The tested devices are NMOS transistors with a 5 nm SiO2 gate oxide and with various gate geometries. View full abstract»

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  • MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology

    Page(s): 67 - 71
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    The influence of interconnects and the pad stack on measured Metal-Oxide-Semiconductor (MOS) transistor parameter and their reliability degradation cannot always be neglected. The underlying effect is Plasma-Induced-Damage (PID) from the parasitic antennas connected to the MOS gate electrode. Usually, a protection diode is employed to avoid this. However, for some stress and measurement sequences a diode at the gate is not desirable. An alternative method - a layout optimisation is presented and discussed. View full abstract»

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  • Hot carrier impact on the small signal equivalent circuit

    Page(s): 72 - 75
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    RF reliability is becoming an increasing concern for actual technology platforms. In this context, small signal equivalent circuit degradation under hot carrier stress is investigated. It is shown that some lumped elements such as the conductance, the transconductance, the gate-to-drain capacitance, and series resistances are degraded. The application of corrections based on physical phenomenon explains the major part of the hot carrier impact on the small signal equivalent circuit. Furthermore, the overlap gate-to-drain capacitance degradation is emphasized. View full abstract»

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