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[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit

23-27 Sept. 1991

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Displaying Results 1 - 25 of 128
  • Test generation algorithms

    Publication Year: 1991, Page(s):T7 - 1/1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (51 KB)

    Summary form only given. Test generation algorithms are algorithms used for computing the test sets for production testing ICs. In this tutorial the author discusses some of the 'state of the art' test generation algorithms for combinational circuits. This is not as restrictive as it first appears if one considers the fact that circuits are being designed using the 'design for testability' rules l... View full abstract»

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  • Proceedings. Fourth Annual IEEE International ASIC Conference and Exhibit (Cat. No.91TH0379-8)

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (12 KB)
    Freely Available from IEEE
  • Partial silicon compilation of recursive digital filters using VHDL

    Publication Year: 1991, Page(s):P8 - 3/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The FOREST computer program for the functional and architectural synthesis of recursive digital filters is described. It outputs a bit-serial architecture in the form of a VHDL netlist that may be used as input of any available logic synthesis and layout tool that accepts VHDL View full abstract»

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  • Behavioral VHDL transistor slope models

    Publication Year: 1991, Page(s):P8 - 4/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Behavioral CMOS transistor models that can accurately predict the timing and logic operation of a custom designed circuit layout are presented. A simple layout extraction program translates the layout netlist to a transistor level VHDL architecture which can be directly simulated, either as a standalone component or as a system module. Simple VHDL constructs and existing delay models were used to ... View full abstract»

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  • Functional block design using VHDL simulation and synthesis

    Publication Year: 1991, Page(s):P8 - 5/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    This is a case study comparison between traditional and VHDL design methods of a small sized logic module (1500 gates). The areas where design cycle improvements and gate count reductions were realized are discussed as well as VHDL development strategies undertaken to reduce the impact of the design tools' limitations View full abstract»

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  • Design considerations for Cross Check foundations and libraries

    Publication Year: 1991, Page(s):P11 - 5/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    CrossCheck built-in test techniques require special structures in Sea-of-Gates foundations and cell personalizations. This paper discusses the performance and area impacts these structures make to gate-array chips and cell libraries. Results from fabricated CrossCheck devices are presented View full abstract»

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  • Feasibility estimation and cost optimization for multichip module technologies

    Publication Year: 1991, Page(s):P9 - 1/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Multichip module (MCM) technologies introduce new levels of complexity in the design and analysis of systems. As a result, feasibility estimation and cost optimization are crucial to a successful design effort. The authors propose an efficient but effective global router based on a multiterminal multicommodity flow model to perform the estimation View full abstract»

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  • Power calculation for CMOS gate arrays

    Publication Year: 1991, Page(s):P12 - 1/1-5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    This paper describes a new procedure to calculate the power consumption of VLSI CMOS Gate Arrays. The system is based on a pre-defined power model library describing the physical behavior of all macros in Motorola's cell library in terms of power dissipation. The short circuit current of the complementary transistors is taken into account. For a specific design first the required circuit data are ... View full abstract»

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  • The pin redistribution problem in multi-chip modules

    Publication Year: 1991, Page(s):P9 - 2/1-4
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors introduce the pin redistribution problem (PRP) which arises in multi-chip modules. The problem is to redistribute the pins of the chip layer onto a uniform grid. The goal is to minimize the number of layers required to redistribute the entire set. As a net is undefined, a number of challenging issues arise. Three effective methods for solving this problem are proposed View full abstract»

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  • A methodology for programmable logic migration to ASICs including automatic scan chain insertion and ATPG

    Publication Year: 1991, Page(s):P2 - 1/1-4
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    Describes a methodology to migrate field programmable logic (FPL) to a gate array or standard cell ASIC with automated schematic translation, functional verification, static timing analysis, and test program generation. The input to the migration flow is the FPL netlist. The translation software replaces existing flip-flops with equivalent scan flip-flops and connects a scan chain. Automatic test ... View full abstract»

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  • AFMG: automatic functional model generation system for digital simulation

    Publication Year: 1991, Page(s):P12 - 2/1-4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    This paper presents an automatic program synthesis system which generates models for digital simulators. Behavioral and structural models are generated from Boolean equations, truth tables, HDL descriptions or schematic diagrams. This system provides an efficient method for automatic model development. As a result, the design cycles can be significantly reduced View full abstract»

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  • Performance evaluation of cascadable built-in tester for large I/O multichip modules

    Publication Year: 1991, Page(s):P9 - 3/1-4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A cascadable built-in tester (CBIT) for testing multichip modules (MCMs) with large number of I/O pins is introduced. The CBIT can function both as a test pattern generator and as a signature analyzer. CBITs are cascadable to produce a maximal length pseudo-random sequence. This sequence yields high fault coverage due to the small signature aliasing probability and the uniqueness of the test patte... View full abstract»

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  • Architectural innovations for high performance in PLDs

    Publication Year: 1991, Page(s):P2 - 2/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Because of the recent explosion of PLD architectures, it is more difficult than ever for users to choose the architecture that will best suit their needs. To aid in that choice, this paper discusses performance trade-offs with respect to features of a PLD, and also examines what to look for when reading data sheets for programmable devices View full abstract»

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  • Using optimization in circuit design to improve the yield and circuit performance

    Publication Year: 1991, Page(s):P7 - 7/1-6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    Circuit simulation, circuit optimization, sensitivity analysis and yield analysis and optimization tools are integrated in the OPSIM system and support a design methodology that improves designer productivity, circuit performance, manufacturing yield and longterm reliability in ICs. Values for circuit parameters are automatically determined to meet a target performance while accounting for process... View full abstract»

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  • Single-layer global routing

    Publication Year: 1991, Page(s):P14 - 4/1-4
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Introduces the single-layer global routing problem, also called homotopic routing. A new technique, Density-Algorithm, is proposed to determine the global routing for each net (if there exists one) such that the number of routed nets are maximized. An optimal postprocessing algorithm, minimizing wire length and number of bends, under homotopic transformation, is presented to further improve the ro... View full abstract»

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  • Triple metal routing methodology for ASIC sea-of-cells design

    Publication Year: 1991, Page(s):P12 - 3/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    This paper presents a general sea-of-cells routing methodology for state-of-the-art ASIC design, where three layers of metal are available for signal interconnection. As routing channels are defined over the cells, this routing system not only deals with various blockages on different layers, but also considers performance constraints such as wire widths and coupling noises for mixed analog/digita... View full abstract»

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  • Memorist: a diffused CMOS SRAM compiler for gate array applications

    Publication Year: 1991, Page(s):P14 - 8/1-5
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A flexible SRAM compiler has been developed to generate high speed, high density, synchronous CMOS memories. The fully diffused single and dual port designs allow for a high level of memory integration into a gate array environment targeted for system solutions. The compiler provides for accurate multi-level timing characterization and is tightly integrated into an ASIC development system. A 4-die... View full abstract»

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  • A multi-chip module substrate testing algorithm

    Publication Year: 1991, Page(s):P9 - 4/1-4
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Discusses substrate short/open fault detection in MCM manufacturing, and propose a complete open fault coverage algorithm which generates a minimum number of tests required to completely cover all open faults. The algorithm generates only about half of the test size compared to that of ordinary approaches. Multi-dimensional TSP algorithms are devised to optimize probe routes with quite encouraging... View full abstract»

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  • A new approach to the problem of PLA partitioning using the theory of the principal lattice of partitions of a submodular function

    Publication Year: 1991, Page(s):P2 - 4/1-4
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    An area efficient 2 level implementation of combinational logic can be achieved by partitioning the original PLA into several PLAs each of which interacts with the others weakly. A PLA implementing a sum of products logic functions can be modelled through a bipartite graph B G, which specifies the intersection of rows (minterms) with columns of the AND plane (primary inputs) an... View full abstract»

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  • A 32-bit CMOS numerically controlled oscillator ASIC exceeds 234 MHz

    Publication Year: 1991, Page(s):P1 - 3/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    A new design technique has been developed and implemented that allows much higher frequencies to be generated using direct digital synthesis (DDS). Using this improved progression-of-states technique, a 32-bit numerically controlled oscillator (NCO) implemented in a 1.0-micron complementary metal oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) gate-array can now accumulat... View full abstract»

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  • FPGA implementation of the BH8000 wormhole router

    Publication Year: 1991, Page(s):P16 - 3/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    A Xilinx FPGA was chosen for prototyping a self-timed message routing device. The authors' experience in implementing an asynchronous design on an FPGA, which like most other programmable logic is optimised for synchronous designs, is described. The manual intervention needed at various stages of design implementation is discussed. Debugging and performance issues are looked at and some modificati... View full abstract»

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  • VHDL-A management overview

    Publication Year: 1991, Page(s):T11 - 1/1-10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The tutorial begins with an outline of the motivation for the development of VHDL. The problems of parts obsolescence and system complexity are enunciated and a hardware description language is proposed as a means of overcoming the problems. There is a demonstration of VHDL meeting the requirements of a HDL namely-communication, modeling capabilities, and semantic completeness. The modeling capabi... View full abstract»

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  • Interconnect testing using BIST embedded in IEEE 1149.1 designs

    Publication Year: 1991, Page(s):P11 - 2/1-4
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    As board and packaging techniques continue to drive to smaller geometries and increased densities, it becomes increasingly difficult to use conventional test techniques to test board interconnect and functionality. Fine-pitch QFPs, TAB packaging and multichip modules limit test accessibility and manufacturing defect detection. Of the typical faults found during manufacturing test of a board (opens... View full abstract»

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  • On clock routing for general cell layouts

    Publication Year: 1991, Page(s):P14 - 5/1-4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Addresses the minimum-skew clock routing problem in general cell designs. The authors present a bottom-up construction method for clock distribution trees based on a generalized matching computation in channel intersection graphs. The clock routing trees produced by their method attain almost zero skew with only modest wirelength penalty. Experimental results show that clock skew of their routing ... View full abstract»

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  • Experimental studies of metastability behaviors of sub-micron CMOS ASIC flip flops

    Publication Year: 1991, Page(s):P7 - 4/1-4
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    The author describes the experiment for characterizing metastability performances of sub-micron gate array and cell-based CMOS ASIC flip flops. Basic metastability theory, metastability test circuit, software (flow charts) and hardware set up are discussed. Analyzed experimental results are compared with other technologies View full abstract»

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