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ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Date 23-27 Sept. 1991

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Displaying Results 1 - 25 of 128
  • Proceedings. Fourth Annual IEEE International ASIC Conference and Exhibit (Cat. No.91TH0379-8)

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (12 KB)
    Freely Available from IEEE
  • Finite state machine optimization algorithms for pipelined data path controllers

    Publication Year: 1991, Page(s):P18 - 7/1-4
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Algorithms for generating an optimal finite state machine (FSM) implementation of pipelined data path controllers are presented. The groups of states are partitioned into two, states are encoded, and each partition is mapped onto one PLA to form a two-PLA based Moore-style FSM state sequencer. The experimental results show that substantial savings in layout area can be achieved compared to publish... View full abstract»

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  • Behavioral VHDL transistor slope models

    Publication Year: 1991, Page(s):P8 - 4/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Behavioral CMOS transistor models that can accurately predict the timing and logic operation of a custom designed circuit layout are presented. A simple layout extraction program translates the layout netlist to a transistor level VHDL architecture which can be directly simulated, either as a standalone component or as a system module. Simple VHDL constructs and existing delay models were used to ... View full abstract»

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  • Low noise digital logic techniques

    Publication Year: 1991, Page(s):T13 - 1/1-2
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    Low-noise digital logic circuits designed to complement conventional static logic in high-speed high-precision mixed-signal applications are reviewed in this paper. By steering constant currents to realize the logic functions, it has been shown that digital switching noise is reduced by about two orders or magnitude which will allow much higher accuracy in mixed-mode ICs View full abstract»

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  • Functional block design using VHDL simulation and synthesis

    Publication Year: 1991, Page(s):P8 - 5/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    This is a case study comparison between traditional and VHDL design methods of a small sized logic module (1500 gates). The areas where design cycle improvements and gate count reductions were realized are discussed as well as VHDL development strategies undertaken to reduce the impact of the design tools' limitations View full abstract»

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  • The Exemplar Logic synthesis system: a logic synthesis tool for field programmable gate arrays

    Publication Year: 1991, Page(s):P13 - 2/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    High density programmable logic devices require dedicated synthesis algorithms to maximize the utilization of the device resources. The authors discuss the impact of device architectures on logic synthesis algorithms, and show how device specific optimization allows designers to design for multiple architectures from a common design description. The Exemplar Logic synthesis system combines industr... View full abstract»

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  • Explicit elimination of easy-to-test faults in a sequential test generator

    Publication Year: 1991, Page(s):P6 - 2/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The authors describe how to eliminate easy-to-test faults after each sequential test vector is generated. The elimination process is conducted using a combinational test generator. Two new classes of faults called 0-step and 1-step testable faults are defined. The percentages of such faults are determined for MCNC benchmark circuits. The CPU time can be up to 150% faster than STEED (a Berkley sequ... View full abstract»

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  • Ground bounce and reduction techniques [CMOS VLSI]

    Publication Year: 1991, Page(s):T13 - 2/1-2
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    VLSI has progressed to reduce the minimum design feature and reduce delay. However, when CMOS circuits rapidly charge or discharge large capacitive loads simultaneously, the corresponding current through the parasitic inductance of the bonding and package lead wiring connecting the chip to one of the power supplies (VDD or VSS) causes a voltage drop to occur. This variation in voltage at the VDD o... View full abstract»

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  • Feasibility estimation and cost optimization for multichip module technologies

    Publication Year: 1991, Page(s):P9 - 1/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Multichip module (MCM) technologies introduce new levels of complexity in the design and analysis of systems. As a result, feasibility estimation and cost optimization are crucial to a successful design effort. The authors propose an efficient but effective global router based on a multiterminal multicommodity flow model to perform the estimation View full abstract»

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  • A color video camera using FPGA video processor

    Publication Year: 1991, Page(s):P16 - 7/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    Describes a color CCD camera with a FPGA video processor for video service. The camera is composed of a CCD imager with [Cy, Gr, Ye; STR] color filter array, scanning and sync. generators, and a digital video processor. The video processors are pipelined and well-designed with the LCA devices (the Xilinx Company's FPGA device), so the system can process a real-time display. The camera can provide ... View full abstract»

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  • ASIC design methodology for conversion of standard products

    Publication Year: 1991, Page(s):P12 - 4/1-2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    There are several advantages in integrating standard products into ASICs. However, the major obstacle has been the tremendous amount of resources required. Because VLSI Technology, Inc. (VLSI) standard products are designed on COMPASS Design Automation design tools, the same tools used by the ASIC divisions in VLSI, the products become much easier to port into the ASIC environment. This paper disc... View full abstract»

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  • High level synthesis of data driven ASICs

    Publication Year: 1991, Page(s):P13 - 3/1-4
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A novel approach to high level synthesis of ASICs based on a data driven execution model is presented. The synthesis procedure is directed at producing highly parallel ASICs providing high throughput through pipelining. The major benefits of the authors' approach are its potential for higher speed, ease of design, ease of verification and testing View full abstract»

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  • A testable model for stoppable clock ASICS

    Publication Year: 1991, Page(s):P6 - 3/1-5
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    A testable model for globally asynchronous ASICs is presented. These circuits operate without a global clock and are useful for pipelined or data-driven architectures. The ASIC can be partitioned into several locally clocked modules and control is distributed throughout these modules. A test methodology is presented which partitions each locally clocked module into synchronous and asynchronous com... View full abstract»

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  • Self-timed digital systems

    Publication Year: 1991, Page(s):T5 - 1/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Self-timed system organization does not require the central clock; the operation of a system progresses upon the commands or signals that are generated immediately after a particular system operation has been executed. This paper presents several implementations of self-timed systems. The performance figures for such systems match those of synchronous systems, but at the cost of added circuitry View full abstract»

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  • High frequency power supply rejection in analog circuits

    Publication Year: 1991, Page(s):T13 - 3/1-2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    The problems concerning the design of complex mixed-mode circuits are discussed. Complex analog circuits, using on-chip amplifiers, switched-capacitor techniques and digital control logic have to deal with noise on the power supply lines. This extra power supply noise can drastically decrease the performance of a system. Therefore interference aspects of power supply noise are discussed in two ana... View full abstract»

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  • Memorist: a diffused CMOS SRAM compiler for gate array applications

    Publication Year: 1991, Page(s):P14 - 8/1-5
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A flexible SRAM compiler has been developed to generate high speed, high density, synchronous CMOS memories. The fully diffused single and dual port designs allow for a high level of memory integration into a gate array environment targeted for system solutions. The compiler provides for accurate multi-level timing characterization and is tightly integrated into an ASIC development system. A 4-die... View full abstract»

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  • Evaluation of a technology for a synchronous application

    Publication Year: 1991, Page(s):P7 - 3/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    A method is discussed describing an initial `first pass' performance evaluation on how well a technology will fit into a system design. The method involves calculating, from the vendor specifications, maximum chip to chip interconnect toggling frequency and internal to the chip, the maximum number of gates that can be inserted in between two latches clocked by the same clock. This method is meant ... View full abstract»

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  • CAE simulation tool selection criteria for today's ASIC designs

    Publication Year: 1991, Page(s):T6 - 1/1-3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    Designers and managers are usually required to make selections of CAE simulation tools in preparation for a new ASIC design start. An often arduous task, as many as three or more vendors can be asked to present their products and demonstrate (either via evaluation or benchmark) the ability to match a set of selection criteria. The author has participated in many of these demonstrations and can att... View full abstract»

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  • Understanding PLD parameter specifications

    Publication Year: 1991, Page(s):P2 - 7/1-3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    Discusses issues of current PLD parameter specification. It covers two specific areas; standardization of PLD specifications and data that could be provided to enhance designers knowledge View full abstract»

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  • Power calculation for CMOS gate arrays

    Publication Year: 1991, Page(s):P12 - 1/1-5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    This paper describes a new procedure to calculate the power consumption of VLSI CMOS Gate Arrays. The system is based on a pre-defined power model library describing the physical behavior of all macros in Motorola's cell library in terms of power dissipation. The short circuit current of the complementary transistors is taken into account. For a specific design first the required circuit data are ... View full abstract»

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  • The pin redistribution problem in multi-chip modules

    Publication Year: 1991, Page(s):P9 - 2/1-4
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors introduce the pin redistribution problem (PRP) which arises in multi-chip modules. The problem is to redistribute the pins of the chip layer onto a uniform grid. The goal is to minimize the number of layers required to redistribute the entire set. As a net is undefined, a number of challenging issues arise. Three effective methods for solving this problem are proposed View full abstract»

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  • MicroSystems education and a `silicon encyclopedia' project

    Publication Year: 1991, Page(s):P17 - 1/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    It is becoming harder to educate and train engineers to design microelectronic systems, both in the University and in industry. New technology (for example field-programmable gate arrays, and other programmable logic devices) and new software (logic synthesis and hardware description languages) for MicroSystem design is arriving at a rapid pace. Silicon technology and the design tools themselves a... View full abstract»

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  • Selection assistant system for gate array user

    Publication Year: 1991, Page(s):P12 - 5/1-4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    The system presented resorts to an expert system technique to assist inexperienced gate array users in the selection process. The system establishes user requirements either through interactive dialogue or by automatic extraction from the schematic View full abstract»

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  • Timing optimization of MOS combinational networks

    Publication Year: 1991, Page(s):P13 - 4/1-4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The authors extend their MOS network optimization algorithm, SYLON-REDUCE, to perform timing optimization. Since optimization is performed in a technology-specific domain, the results should more closely reflect the actual improvement in the delay of the network. They also propose a delay model that takes into account the largest number of serially-connected transistors, as well as the number of f... View full abstract»

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  • An ASIC level BIST implementation for system level testing

    Publication Year: 1991, Page(s):P6 - 4/1-4
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    The architecture and operation of a built-in self-test (BIST) implementation at the ASIC level for use at manufacturing unit level testing and system diagnostics is described. Analysis of this BIST approach is given in terms of area overhead, fault coverage, reduction in manufacturing testing costs, and reduction in system diagnostic execution time View full abstract»

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