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ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Date 23-27 Sept. 1991

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Displaying Results 1 - 25 of 128
  • Proceedings. Fourth Annual IEEE International ASIC Conference and Exhibit (Cat. No.91TH0379-8)

    Publication Year: 1991
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    Freely Available from IEEE
  • FISTEM: a CAD tool for synthesis of easily testable FSM

    Publication Year: 1991 , Page(s): P6 - 5/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (316 KB)  

    In this paper the authors propose a new system named FISTEM for testability synthesis and test generation of PLA-based finite state machines. A nonscan design methodology, based on constrained state assignment and logic optimization, is used which guarantees testability for all combinationally irredundant crosspoint faults in the PLA. Test sequences for these faults are obtained using combinationa... View full abstract»

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  • Clock layout for high-performance ASIC based on weighted center algorithm

    Publication Year: 1991 , Page(s): P15 - 5/1-4
    Cited by:  Papers (4)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (280 KB)  

    A new clock distribution scheme is investigated using weighted center algorithm. The algorithm is based on optimum matching of the closest clock terminals and recursively building a clock tree which connects all the clock terminals. The novel feature of the authors' approach is simultaneous minimizing of the clock skew and the total clock tree wire length, and suitable for any design style. Experi... View full abstract»

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  • An ASIC level BIST implementation for system level testing

    Publication Year: 1991 , Page(s): P6 - 4/1-4
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (312 KB)  

    The architecture and operation of a built-in self-test (BIST) implementation at the ASIC level for use at manufacturing unit level testing and system diagnostics is described. Analysis of this BIST approach is given in terms of area overhead, fault coverage, reduction in manufacturing testing costs, and reduction in system diagnostic execution time View full abstract»

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  • Gate arrays simplify translation between high speed logic families

    Publication Year: 1991 , Page(s): P9 - 6/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (304 KB)  

    TTL dominates todays I/O specifications. However, ECL logic provides increased bandwidth and low noise in a transmission line environment. High performance designs increasingly need to combine ECL and TTL interfaces. This paper presents a flexible approach to mixed signal level translations (ECL/PECL and TTL) utilizing a single I/O cell on a family of ECL gate arrays. The incorporation of Schottky... View full abstract»

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  • Radiation and life test procedures for military and aerospace ASIC components

    Publication Year: 1991 , Page(s): P4 - 5/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (248 KB)  

    Presents part qualification, characterization and test/screening procedures for ASICs, intended for military and aerospace use. These procedures provide quick and low cost evaluation of commercial technology transferred to mil/aerospace systems View full abstract»

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  • Timing issues related to the automated placement and routing of high performance ASICs

    Publication Year: 1991 , Page(s): P14 - 6/1-4
    Cited by:  Patents (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (352 KB)  

    Discusses the timing issues and methodologies involved in the automated placement and routing of high speed ASICs. As device sizes shrink and clock speeds increase, timing driven layout becomes critical in meeting time-to-market deadlines. The concepts covered include clock tree synthesis, net timing constraints, critical path timing constraints, pin-to-pin delay calculation and back-annotation View full abstract»

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  • A fast implementation of the distributed arithmetic discrete Fourier transform

    Publication Year: 1991 , Page(s): P3 - 7/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (280 KB)  

    A new DFT implementation incorporating distributed arithmetic with the DFT is reported. This method proves to be faster and to require less area than the direct implementation of the FFT View full abstract»

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  • Architectural innovations for high performance in PLDs

    Publication Year: 1991 , Page(s): P2 - 2/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (272 KB)  

    Because of the recent explosion of PLD architectures, it is more difficult than ever for users to choose the architecture that will best suit their needs. To aid in that choice, this paper discusses performance trade-offs with respect to features of a PLD, and also examines what to look for when reading data sheets for programmable devices View full abstract»

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  • CAE techniques for GaAs ASIC design

    Publication Year: 1991 , Page(s): P15 - 1/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (452 KB)  

    Discusses CAE techniques which have been utilized in applying `standard' CAE tools to a somewhat nonstandard design situation-the creation of extremely high-speed digital integrated circuits on gallium arsenide substrates. This paper will concentrate chiefly on those aspects which are unique to this endeavor-the extremely high edge and data rates, for example-and the behaviors of the standard tool... View full abstract»

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  • Routability design for sea-of-cells

    Publication Year: 1991 , Page(s): P14 - 3/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (324 KB)  

    The routability design of a core cell for three layer sea-of-cells is discussed. A formula to estimate both horizontal and vertical routing tracks in a core cell is derived. The estimation is based on average pin counts per base cell, and the number of rows and columns of base cells in an array. The formula has been applied to a series of bipolar and BiCMOS array families. The accuracy of the pred... View full abstract»

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  • Stimulus generation using the test pattern development language

    Publication Year: 1991 , Page(s): P15 - 4/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (300 KB)  

    Stimulus generation is one of the more challenging tasks in IC design. The Test Pattern Development Language (TPDL) simplifies this process by guaranteeing that simulation patterns are correctly constructed for direct use by the tester. TPDL provides a generic interface which can be used on multiple platforms. The creation of complex stimuli is facilitated via the high level language constructs co... View full abstract»

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  • A sub-micron ECL gate array family

    Publication Year: 1991 , Page(s): P9 - 5/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (208 KB)  

    A new ECL gate array family was developed with 50ps typical gate delay under 1 mA switching current. It pushes the gate count to over 100K gates with 320 I/O signal pads. The process used is National Semiconductor's fourth generation, 0.8 μm ASPECT III process. A frequency divider test with 0.6mA switching current was used to prove the input frequency exceeds 2.5 GHz for the first time utilizin... View full abstract»

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  • A vertically integrated test methodology based on JTAG IEEE 1149.1 Standard Interface

    Publication Year: 1991 , Page(s): P11 - 4/1-4
    Cited by:  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (376 KB)  

    A vertically integrated test methodology has been developed for ASIC testing based on the IEEE 1149.1 Standard Test Interface. A common interface is used to test at the wafer, packaged-chip and board/system levels. The boundary scan JTAG interface is combined with an internal full scan based test technique to provide a uniform test procedure at all stages of testing. At the prototype debug phase, ... View full abstract»

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  • Implementation of a high-speed FIR filter using a BiCMOS-ECL mixed gate array with embedded SRAM

    Publication Year: 1991 , Page(s): P3 - 6/1-4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (224 KB)  

    Describes several options of implementing a finite impulse response (FIR) digital filter. A design example of a FIR filter using a single high-speed multiplier/accumulator and embedded BiCMOS SRAMs in a BiCMOS-ECL gate array is presented View full abstract»

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  • ASIC design system for radiation environments

    Publication Year: 1991 , Page(s): P4 - 4/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (340 KB)  

    A complete radiation hardened ASIC design system, under development by a three company team is described. The compiler approach design system, with radiation hardness tunable library cells, allows the designer to concentrate on the circuit design rather than the details of hardness affecting geometry layout. The designer must be aware of the hardness requirements and the limitations of the availab... View full abstract»

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  • A large dynamic range photodetector array for acousto-optic spectrum analyzers

    Publication Year: 1991 , Page(s): P4 - 7/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (316 KB)  

    Discusses the design considerations involved in the practical application of the wide dynamic range photodetector technology to a spectrum analyzer intended for use in a Radar Electronic Support Measures (RESM) system. A 128 element photodetector array developed for this application is described View full abstract»

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  • Random walks for circuit clustering

    Publication Year: 1991 , Page(s): P14 - 2/1-4
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (372 KB)  

    The authors introduce a fast, parallelizable approach to circuit clustering based on analysis of random walks in the netlist. The method yields good clustering solutions for classes of `difficult' inputs in the literature as well as for industry benchmark circuits. The authors characterize their results using a new clustering metric which facilitates comparison with future work. Extensions to a nu... View full abstract»

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  • Two 30 K transistor, 165 MHz ASICs for high speed data transmission

    Publication Year: 1991 , Page(s): P1 - 7/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (308 KB)  

    Two 0.9 micron CMOS devices are described which perform multiplexing, demultiplexing, encoding and decoding in transmission equipment. The devices operate at 165 MHz, interface with 100 K ECL I/O, dissipate less than 1 watt each and in total replace 12 bipolar ECL parts View full abstract»

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  • Fast partitioning method for PLA-based architectures

    Publication Year: 1991 , Page(s): P2 - 3/1-4
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (328 KB)  

    Describes a method for automatic partitioning of a given multioutput function into the smallest number of subfunctions such that each subfunction can fit into a fixed size PLA or functional block of a given field programmable gate array (FPGA) chip. The proposed method is fast, efficient and produces almost optimum partitions for the examples which have been tried. The partitioning procedure is in... View full abstract»

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  • ASIC applications in computed tomography systems

    Publication Year: 1991 , Page(s): P1 - 3/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (240 KB)  

    Describes the uses of application-specific integrated circuits (ASICs) in computed tomography (CT) diagnostic imaging systems, CT scanners currently in production and future systems under development use the full range of ASIC technologies, from field-programmable gate arrays (FPGAs) to full-custom mixed-signal integrated circuits. Criteria for determining when to use ASICs and what type of ASIC t... View full abstract»

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  • Embedded test structures reduce ASIC time-to-market

    Publication Year: 1991 , Page(s): P7 - 6/1-3
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (216 KB)  

    LSI Logic Corporation, using embedded test circuitry developed by CrossCheck Technology Inc., has developed a new compacted array technology known as the LFT150K FasTest Array series. The author gives a brief overview of the LFT150K family, describe the performance impact of the embedded test structures, compare this test scheme with conventional scan methods, and describe the FasTest time-to-mark... View full abstract»

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  • A high-performance LED array driver ASIC with programmable thermal coefficients

    Publication Year: 1991 , Page(s): P5 - 4/1-2
    Cited by:  Patents (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (176 KB)  

    The authors describe the design of an LED driver ASIC for use in a high-performance printing system using advanced CMOS technology. This ASIC provides digitally controllable constant-current sources capable of delivering up to 6 mA to each channel of an array of 96 LEDs with an effective 16-bit resolution. It features automatic in-situ temperatures compensation with field programmable temperature ... View full abstract»

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  • ASIC design in a mixed-tool environment

    Publication Year: 1991 , Page(s): P12 - 6/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (244 KB)  

    Today's ASIC designers use a wide variety of tools from multiple CAE vendors, covering the full spectrum of design abstractions. This paper discusses ASIC design in a mixed-tool environment from both the designer's and the ASIC vendor's perspective View full abstract»

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  • A BiCMOS tristate buffer for high-speed microprocessor VLSI

    Publication Year: 1991 , Page(s): P10 - 5/1-4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (164 KB)  

    This paper presents a high speed BiCMOS tristate buffer with a single bipolar device pull-up structure for driving a bus with a large capacitive load. With the new pull-structure, the BiCMOS tristate buffer, which is suitable for microprocessor VLSI, has an improvement in delay time of 30% compared with the standard BiCMOS tristate buffer View full abstract»

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