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Date 1-4 Dec. 2010

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Displaying Results 1 - 25 of 86
  • [Front cover]

    Publication Year: 2010, Page(s): C1
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  • [Title page i]

    Publication Year: 2010, Page(s): i
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  • [Title page iii]

    Publication Year: 2010, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2010, Page(s): iv
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  • Table of contents

    Publication Year: 2010, Page(s):v - xi
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  • Message from the General Chair

    Publication Year: 2010, Page(s): xii
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  • Message from the Program Co-chairs

    Publication Year: 2010, Page(s): xiii
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  • Organizing Committee

    Publication Year: 2010, Page(s):xiv - xvi
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  • list-reviewer

    Publication Year: 2010, Page(s): xvii
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  • Special Panel Session

    Publication Year: 2010, Page(s): xviii
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  • Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

    Publication Year: 2010, Page(s):3 - 8
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    In recent technology nodes, reliability is considered a part of the standard design ¿ow at all levels of embedded system design. While techniques that use only low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently eva... View full abstract»

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  • Jitter Characterization of Pseudo-random Bit Sequences Using Incoherent Sub-sampling

    Publication Year: 2010, Page(s):9 - 14
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2196 KB) | HTML iconHTML

    In this paper, jitter analysis algorithms for characterizing timing jitter of multi-Gbps pseudo-random bit sequences (PRBSs) are presented. For signal acquisition, incoherent sub-sampling is employed to increase the effective sampling rate of a digitizer and to simplify its signal acquisition architecture by removing the need for timing synchronization circuits. As a substitute for these circuits,... View full abstract»

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  • FSimGP^2: An Efficient Fault Simulator with GPGPU

    Publication Year: 2010, Page(s):15 - 20
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (282 KB) | HTML iconHTML

    General Purpose computing on Graphical Processing Units (GPGPU) is a paradigm shift in computing that promises a dramatic increase in performance. But GPGPU also brings an unprecedented level of complexity in algorithmic design and software development. In this paper, we present an efficient parallel fault simulator, FSimGP2, that exploits the high degree of parallelism supported by a s... View full abstract»

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  • A Quasi-best Random Testing

    Publication Year: 2010, Page(s):21 - 26
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (146 KB) | HTML iconHTML

    Random testing, having been employed in both hardware and software for a long time, is well known for its simplicity and straightforwardness, in which each test is selected randomly regardless of the tests previously generated. However, traditionally, it seems to be inefficient for its random selection of test patterns. Therefore, a new concept of quasi-best distance random testing is proposed in ... View full abstract»

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  • Testing of Low-Cost Digital Microfluidic Biochips with Non-regular Array Layouts

    Publication Year: 2010, Page(s):27 - 32
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (331 KB) | HTML iconHTML

    Digital micro fluidic biochips with non-regular arrays are of interest for clinical diagnostic applications in a cost-sensitive market segment. Previous techniques for biochip testing are limited to regular micro fluidic arrays. We present an automatic test pattern generation (ATPG) method for non-regular digital micro fluidic chips. The ATPG method can generate test patterns to detect catastrophi... View full abstract»

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  • Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits

    Publication Year: 2010, Page(s):33 - 38
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB) | HTML iconHTML

    Logic synthesis of reversible circuits has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-ga... View full abstract»

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  • On Determining the Real Output Xs by SAT-Based Reasoning

    Publication Year: 2010, Page(s):39 - 44
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (338 KB) | HTML iconHTML

    Embedded testing, built-in self-test and methods for test compression rely on efficient test response compaction. Often, a circuit under test contains sources of unknown values (X), uninitialized memories for instance. These X values propagate through the circuit and may spoil the response signatures. The standard way to overcome this problem is X-masking. Outputs which carry an X value are usuall... View full abstract»

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  • On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing

    Publication Year: 2010, Page(s):45 - 48
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (161 KB) | HTML iconHTML

    Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization... View full abstract»

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  • Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment

    Publication Year: 2010, Page(s):53 - 56
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB) | HTML iconHTML

    In this paper we are revisiting the issue of sequential circuit test generation, and use a selective random pattern test generation method implemented in an HDL environment. The method uses a statistical expectation graph and states of the sequential circuit for selecting the appropriate test vectors to achieve better fault coverage and a more compact test set. To further reduce the size of the ge... View full abstract»

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  • Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs

    Publication Year: 2010, Page(s):59 - 64
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    Symbolic techniques have been shown to be very effective in path-based test generation, however, they fail to scale to large programs due to the exponential number of paths to be explored. In this paper, we focus on tackling this path explosion problem and propose search strategies to achieve quick branch coverage under symbolic execution, while exploring only a fraction of paths in the program. W... View full abstract»

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  • A Reliability Model for Object-Oriented Software

    Publication Year: 2010, Page(s):65 - 70
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (159 KB) | HTML iconHTML

    Software reliability is one of the important attributions of dependable systems. A number of software reliability models have been developed by now, but few of them take object-oriented features into account. Nowadays, more and more software systems are developed in object-oriented technology and object-oriented programming languages contain new language features, most notably inheritance, polymor... View full abstract»

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  • A New Approach to Generating High Quality Test Cases

    Publication Year: 2010, Page(s):71 - 76
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (351 KB) | HTML iconHTML

    High quality test cases can effectively detect software errors and ensure software quality. However, except the regular expression-based test generation method, test cases generated from other model-based test generation methods have not contain the whole information of the model, resulting in test inadequacy. And test cases derived from regular expression have the prohibited lengths that cause th... View full abstract»

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  • A Study on Software Reliability Prediction Based on Transduction Inference

    Publication Year: 2010, Page(s):77 - 80
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB) | HTML iconHTML

    Non-parametric statistical methods are applied to verdict that early failure behavior of the testing process may have less impact on later failure process, so it happens in software failure time prediction that one does not have enough information to estimate the software failure process well but do have enough information to estimate the failure data at given instance. The prediction accuracy of ... View full abstract»

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  • Formula-Oriented Compositional Minimization in Model Checking

    Publication Year: 2010, Page(s):81 - 84
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    This paper presents a new approach to reduce finite state machines with respect to a CTL formula to alleviate state explosion problem. Reduction is achieved by removing parts useless to the formula of original machines. The main contribution of this paper is to exploit relations among sub formulas of the CTL formula so as to gain more reduction, as well as to extend traditional pruning method, whi... View full abstract»

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  • Variation-Aware Fault Modeling

    Publication Year: 2010, Page(s):87 - 93
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical li... View full abstract»

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