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SoC Design Conference (ISOCC), 2010 International

Date 22-23 Nov. 2010

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Displaying Results 1 - 25 of 112
  • Noise management in highly heterogeneous SoC based integrated circuits

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (201 KB) |  | HTML iconHTML  

    Noise coupling is one of the most fundamental issues in the design of highly heterogeneous, robust integrated systems. A two-step noise management methodology is proposed in this paper. In the first step, a methodology is described to efficiently analyze noise coupling in large scale circuits while maintaining sufficient accuracy. The second step consists of a methodology to significantly mitigate switching noise. The first step helps determining the required signal isolation and the efficacy of the noise reduction technique proposed in the second step. The two primary noise coupling paths in hybrid systems utilizing three dimensional (3-D) integration technology are also identified. View full abstract»

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  • Power gated SRAM circuits with data retention capability and high immunity to noise: A comparison for reliability in low leakage sleep mode

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (142 KB) |  | HTML iconHTML  

    A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by up to 3.84× and the read static noise margin is increased by up to 4.79× with the new memory power gating technique as compared to a previously published power gated 6T SRAM circuit in a UMC 80nm CMOS technology. View full abstract»

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  • How forward body bias helps to reduce ground bouncing noise and silicon area in MTCMOS circuits: Divulging the basic mechanism

    Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    Forward body bias is an effective technique for reducing mode transition noise and area overhead associated with Multi-threshold CMOS (MTCMOS) circuits. In this paper, the principal mechanism of noise reduction and silicon area compaction in forward-body-biased MTCMOS circuits is revealed and discussed in detail. Tradeoffs between area and leakage power consumption in forward-body-biased MTCMOS circuits are evaluated. Design guidelines are provided for optimum sizing of noise-control transistor and appropriate selection of body bias voltage to fully utilize the benefits of the forward body bias technique. View full abstract»

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  • UWB SoC co-design with ESD protection

    Page(s): 13 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB) |  | HTML iconHTML  

    This paper discusses critical aspects for co-design of ultra wideband (UWB) system-on-chip (SoC) and on-chip electrostatic discharge (ESD) protection, which are beyond simple data rate and bandwidth considerations. UWB-ESD co-design techniques and experiment results are presented. The designs were implemented in a commercial 0.18 μm RFCMOS. View full abstract»

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  • Noise reduction communication circuits

    Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (401 KB) |  | HTML iconHTML  

    The demand for longer battery life and faster speeds for communications circuits coupled with the exponential expansion of wireless communications devices is creating increasingly serious noise problems for communications circuits. Longer battery life means lower power consumption usually obtained by reduced noise margins that can only be achieved by better circuit design, but at least this under the designer's control. Demand for more spectrum by the explosion of wireless devices creates noise sources outside the designer's control that must be dealt with by increasingly clever noise attenuation circuits. This paper will review the state of the art for adaptive filtering as applied to external noise attenuation in communication circuits highlighting the most promising technologies including adaptive heterodyne filters. View full abstract»

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  • Impact of low-doped substrate areas on the reliability of circuits subject to EFT events

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (662 KB) |  | HTML iconHTML  

    External stresses, such as those generated due to Electrical Fast Transient (EFT) events, generate over-voltages which may result in reliability failures at the IClevel either in the form of recoverable or permanent damage of the IC. In the present paper, the relationship between the technology characteristics within a design framework and the permanent failures that such an EFT event can produce are discussed. Solutions to minimize the impact of such EFT events are presented. View full abstract»

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  • A VGA CMOS Image Sensor with 11-bit column parallel single-slope ADCs

    Page(s): 25 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (166 KB) |  | HTML iconHTML  

    In this paper, CMOS Image Sensor (CIS) for VGA is presented. It has 11-bit column parallel single-slope ADCs. Single slope ADC is suitable for column parallel ADC of CIS. This CIS is fabricated in 0.13μm CMOS process. Its pixel size is 2.25 × 2.25 μm2. Total chip area is 5×5 mm. Its analog power consumption is 42.9 mW and digital power consumption is 1.6 mW. View full abstract»

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  • Image noise reduction by dynamic thresholding of correlated wavelet intensity and anisotropy

    Page(s): 28 - 33
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB) |  | HTML iconHTML  

    A novel image noise reduction filter is developed in wavelet domain. The correlations of intensity and anisotropy of wavelet coefficients in different sub-bands and scales are utilized as features to separate signal from random noise. Dynamic thresholding is used to further increase the sensitivity and discrimination against different noise patterns and standard deviations. Simulation in Matlab is carried out by filtering an AWGN-added sub-set of test images from Kodak image data base and a standard digital Macbeth Color Chart. Average PSNR scores of R, G and B color channels are competitive to bilateral filter and a prominent commercial noise reduction tool Neat Image. In addition, the low computational complexity of threshold operation makes it applicable for low cost implementations in various imaging devices as a real time noise reduction module. View full abstract»

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  • Weighted image defogging method using statistical RGB channel feature extraction

    Page(s): 34 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (314 KB) |  | HTML iconHTML  

    In this paper, we present a weighted adaptive image defogging method by extracting features in the RGB color channels. We adaptively detect an atmospheric light through undesired fog in the dark channel prior obtained in the YCbCr color channels and generate a transmission map based on the detected atmospheric light. We adaptively remove the fog by applying the color correction algorithm based on the feature extraction in the RGB color channels. The proposed algorithm can overcome the problem of local color distortion, which is known to be the limitations of existing defogging techniques. Experimental results demonstrate that the proposed algorithm can remove image degradation caused by fog, clouds, smoke, and dust in digital imaging devices. View full abstract»

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  • Adaptive bilateral filtering for noise removal in depth upsampling

    Page(s): 36 - 39
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    3D scene rendering requires depth maps and color information to produce high quality 3D results. Unfortunately, depth maps captured with the Time-of-flight (TOF) cameras have limited resolution and poor image quality, being severely influenced by the random and systematic noise, which makes them inapposite for generating high quality 3D images. In this paper, we have further analyzed a framework for upsampling the resolution of depth maps that jointly uses Gaussians of spatial and depth differences of low resolution depth map's pixels along with Gaussian of color intensity difference from high resolution 2D color image of the same scene. The variance of the Gaussian functions controls the amount of smoothing in uni-planner area and sharpness at boundaries. Using bigger variance smooths uni-planner area but blurs edges and vice versa. We have devised a method to adaptively calculate and use variance to get smoother surface and sharper edges of upsampled depth map with minimized noise. View full abstract»

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  • Image enhancement through weighting function estimation with infrared image

    Page(s): 40 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (410 KB) |  | HTML iconHTML  

    This work presents an efficient image fusion of the visible range (VR) and infrared range (IR) images for image enhancement in digital still camera. Fusion is achieved by estimating the weighting parameters which contain the properties of IR image and by combining the VR and IR images using the parameters. Specifically, the weighting parameters are calculated from the estimated illumination and detail components by a weighted low pass filter (WLPF). In addition, for a user preference, we compress dynamic range of the fused image using a retinex technique and adjust contrast/color based on global color distribution. Experiment results show that the proposed scheme produces good outcomes in terms of visual observation and numerical score. View full abstract»

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  • Nerual signal recorder with tunable gain amplifier using low transconductance OTA

    Page(s): 43 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB) |  | HTML iconHTML  

    In this paper, multi-channel neural signal recorder with tunable gain filter is proposed. It is characterized by small-gm OTA for lowering cutoff frequency. The prototype of the proposed system is designed in TSMC 0.18 μm CMOS technology. Filter consists of high pass filter of delta-gm structure OTA with 201.06 pA/V transconductance and tunable gain Gm-C low pass filter. Single slope ADC is used to convert filter output into digital bits. The tunable gain range, bandwidth, CMRR and input referred noise of resulting filter are 20-68 dB, 20 Hz-10 kHz, 185.7 dB at 5 kHz and 319 nV/VHz, respectively. Single slope ADC has 40 kS/s sampling rate and 1.2 V input range. Total power consumption per channel is 59 μW. View full abstract»

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  • Performance maximization of 3D-stacked cache memory on DVFS-enabled processor

    Page(s): 47 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (623 KB) |  | HTML iconHTML  

    3D integration increases chip integration density, reduces wire length, wire delay and power consumption on wires. However, increased power density causes increase of temperature, which results in the increase of leakage power consumption and performance degradation. In this paper, we propose a solution to compromise these issues on stacking cache memory on a processor core. Experimental results have shown that the proposed method yields, on the average, 16% performance improvement in terms of instructions per second compared to conventional method. The proposed method also reduces energy consumption by 20% on average, in terms of energy per instruction. View full abstract»

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  • A novel dead-time generation method of clock generator for resonant power transfer system

    Page(s): 51 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB) |  | HTML iconHTML  

    This paper presents a novel dead-time generation method of the clock generator for the resonant converter system. The new dead-time generator, which is incorporated to implement the accurate dead-time independent of the output frequency of the clock generator, is designed to prevent cross conduction problem for half-bridge type resonant converter circuit. Dead-time variation range is from 50 ns to 2 μs. View full abstract»

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  • An area efficient programmable built-in self-test for embedded memories using an extended address counter

    Page(s): 59 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (131 KB) |  | HTML iconHTML  

    Programmable memory built-in self-tests (BIST) have increased test flexibility but result in large area overhead. In this research, a new finite state machine (FSM) based programmable memory BIST that can select march algorithms was proposed in order to overcome this problem. The proposed BIST efficiently generates various march algorithms utilizing an extended address counter while also taking into consideration the characteristics of the march algorithms. The experimental results of this research indicated that the proposed BIST improved test flexibility and resulted in a smaller area overhead, as compared to the results of previous studies. View full abstract»

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  • Using dynamic voltage scaling for energy-efficient flash-based storage devices

    Page(s): 63 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB) |  | HTML iconHTML  

    NAND flash memory is commonly known as a power-efficient storage medium. Because of the increasing complexity of flash-based storage devices, however, it is more difficult to achieve good power-efficiency without considering an energy-efficient storage device design. In this paper, we investigate the potential benefit of dynamic voltage/frequency scaling (DVFS) on the energy-efficiency of flash-based storage devices. We first develop a performance/power model for a flash device by using an FPGA-based flash device platform. We then propose a simple DVFS heuristic algorithm that exploits workload fluctuations of a flash device to achieve a significant reduction in energy consumption without performance degradation. Experimental results show that a flash device with DVFS can reduce energy consumption by up to 20%-30%. View full abstract»

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  • DCT-based scheme to accelerate multimedia search in NAND Flash memories

    Page(s): 67 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (310 KB) |  | HTML iconHTML  

    NAND Flash memories are gaining popularity due to their high density, robustness, low power consumption and low read times. Searching data in NAND flash memory is fast for small memory sizes but as the memory size increases, searches become painfully slow. With increased user content inclining towards large multimedia such as images, audio and video, there is a need for faster multimedia content searches (MCS). In this paper we develop a hardware based enhancement technique for fast multimedia content searches in NAND Flash memories. The central idea is to compress the multimedia data by applying Discrete Cosine Transform (DCT) and storing selected coefficients as signatures in the spare blocks of the memory. When a multimedia search request comes in, a signature of the search request is computed and only the signature blocks are compared for a match, thus making faster searches. DCT-based compression gives good results for text, audio, image and video files. If a small part of a multimedia data is given as search request, this technique returns all possible matches found in the set of files stored in the flash memory. Applications of this technique can be found in entertainment industry, music libraries, face recognition etc. Simulations are run for memories between size 2Gb to 16Gb. A speed-up of 450X in the search operation is achieved with this technique. The additional hardware has no performance impact on read or sequential writes of memory. The hardware overhead is estimated to be 0.03% of the total memory area. View full abstract»

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  • Towards practical high-level synthesis from large behavioral descriptions

    Page(s): 71 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (317 KB) |  | HTML iconHTML  

    This paper presents two sets of our recent works towards practical high-level synthesis from large behavioral descriptions: one optimally partitions input behavioral descriptions considering the controller's complexity of synthesized circuits, and the other enhances clock frequency of the circuits by aggressively removing MUXs inserted before registers. These works can further advance the high-level synthesis technology. View full abstract»

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  • Generation of application-domain Specific Instruction-set Processors

    Page(s): 75 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (158 KB) |  | HTML iconHTML  

    This paper introduces a generation method of Application-domain Specific Instruction-set Processors (ASIP) and shows an design example. ASIP is a processor which has some extended instructions specific to application domain. First, advantage of ASIC is explained. Then, some processor generation approaches explained, and an ASIP development environment called ASIP Meister is introduced. Finally, design example shows some effectiveness of ASIP. View full abstract»

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  • Advanced SystemBuilder: A tool set for multiprocessor design space exploration

    Page(s): 79 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB) |  | HTML iconHTML  

    This paper presents our integrated system-level design tool set, named Advanced SystemBuilder. Advanced SystemBuilder supports overall methodology for system design and design space exploration, and provides programming model of systems, automatic synthesis capabilities for FPGA-based prototyping, cosimulation and execution profiling. A case study of MPEG4 decoder design shows the effectiveness of the design space exploration methodology with Advanced SystemBuilder. View full abstract»

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  • Model-based SoC design using ESL environment

    Page(s): 83 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (701 KB) |  | HTML iconHTML  

    With the rising complexities of SoC (Systems-on-Chip), the design community has been searching for new methodology that can handle the given complexities with increased productivity and decreased times-to-market. Electronic system-level (ESL) design is becoming a promised key solution in SoC design, software and hardware must be developed together, however, both software and hardware designers have different views of the system and they use different design/modeling techniques and tools. In this paper, we show an integrated ESL environment for model-based SoC design which supports from algorithm specification modeling by Simulink and synthesizing both software and hardware of SoC by using the combination of several commercialized ESL tools. We also show the design case of video autofocus control unit for the security camera system by using the ESL environment. View full abstract»

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  • System scheduling analysis for high definition multiview video encoder

    Page(s): 87 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB) |  | HTML iconHTML  

    In recent years, 3D related applications, including 3D movie and 3DTV, are getting more and more attentions. In order to make the real-time 3D applications feasible, efficient multiview video coding (MVC) scheme is desired. However, the system throughput requirement on a high definition (HD) MVC encoder is at least two times higher than the current highest throughput H.264/AVC encoder design. In order to meet the target HD MVC specifications, the system scheduling analysis for the HD MVC encoder is performed in this paper. By the 8-stage MB pipeline system architecture with view-parallel MB-interleaved system scheduling and other in-core computation optimizations, the proposed HD MVC encoder design provides about 339% to 1536% higher system throughput than the previous HD H.264/AVC encoder chips and therefore the real-time HD MVC encoding can be achieved. View full abstract»

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  • A synchronization profiler for hybrid full system simulation platform

    Page(s): 91 - 94
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (126 KB) |  | HTML iconHTML  

    A hybrid abstraction of a full system simulation platform can provide flexible hardware-and-software co-verification and co-simulation in early stage of system-on-a-chip development. Being a hybrid abstraction for the simulated system, it has the advantage of faster simulation speed; however, its lack of timing information and no performance-metric synchronization mechanism among the different abstraction levels of the simulation models present troubles in doing performance analysis. To facilitate performance evaluations for hybrid abstraction simulation systems, in this paper, we propose a synchronization profiler to enable cross-abstraction level performance analysis and at the same time retain the fast simulation advantage. This approach allows a design engineer to evaluate not only the interactions between an application and its accelerated hardware but also the corresponding device drivers as well as the OS kernel. View full abstract»

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  • Coarse-grained reconfigurable image stream processor architecture for high-definition cameras and camcorders

    Page(s): 95 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    The coarse-grained reconfigurable image stream processor (CRISP) architecture is introduced for the image processing demands of high-definition (HD) cameras and camcorders. With several architectural concepts of the reconfigurable architecture, the CRISP architecture is proposed to meet the performance and flexibility requirements of the HD cameras. A multi-frame processing system with CRISP is implemented to achieve the real-time HD video recording and 11M-pixel image processing capability. Compared with the performance of the high-dynamic-range image fusion algorithm implemented with a general-purpose processor, 106 times speed-up is achieved by the proposed processor with high image quality of 42.5dB in PSNR. View full abstract»

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  • Implementation of channel estimation for MIMO-OFDM systems

    Page(s): 99 - 102
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    In modern Wireless Local Area Network (WLAN), both the transmitting data throughput and the connecting stability are very important. For the IEEE802.11n protocol specification, it is made of a multi-input multi-output (MIMO) system and an Orthogonal Frequency Division Multiplexing (OFDM) system. In order to decrease the decoding error rate at the receiving end and to fully restore the original transmitting signal, estimation of the channel response information is necessary. In this paper, a combined channel estimation algorithm is proposed by using TDT-L-STBC, which can increase the MIMO channel estimation performance. The proposed architecture of MIMO-2×2 is implemented and verified by TSMC 0.18 μm CMOS technology. View full abstract»

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