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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

1-4 Nov. 2010

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  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Title page]

    Publication Year: 2010, Page(s): 1
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  • [Copyright notice]

    Publication Year: 2010, Page(s): 1
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  • Welcome from the conference co-chairs

    Publication Year: 2010, Page(s): 1
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  • Conference organizations

    Publication Year: 2010, Page(s):1 - 8
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  • ICSICT-2010 sponsorship

    Publication Year: 2010, Page(s): 1
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  • Contents

    Publication Year: 2010, Page(s):I - LX
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  • Directions for silicon technology as we approach the end of CMOS scaling

    Publication Year: 2010, Page(s): 3
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    Summary form only given: CMOS at the 45 nm node has been in production for a couple of years now, and 32 nm CMOS is making its way into leading-edge products. If everything goes according to plan, CMOS at the 11 nm node should be in production in less than ten years from now. However, every technology has its limits and CMOS is no exception. While there will be billions of CMOS devices on a chip, ... View full abstract»

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  • Self-powered nanosystem: From nanogenerators to piezotronics

    Publication Year: 2010, Page(s): 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB) | HTML iconHTML

    In this paper a new approach for converting nano-scale mechanical energy into electric energy by piezoelectric zinc oxide nanowire arrays is discussed. The operation mechanism of the nanogenerator relies on the piezoelectric potential created by an external strain; a dynamic straining of the nanowire results in a transient flow of the electrons in the external load due to the driving force of the ... View full abstract»

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  • Technologies for embedded processors and applications for intelligent control

    Publication Year: 2010, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (262 KB) | HTML iconHTML

    Advances in algorithms combined with ever increasing cost effective computational power is enabling embedded processing solutions to change the world as we know it today. The electrification of the automobile transforming mechanical systems to electronic control as well as the development of alternatives to internal combustion engines, the transformation of the health care system from a centralize... View full abstract»

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  • Overview of advanced Non-Volatile Memory technology

    Publication Year: 2010, Page(s): 6
    Cited by:  Papers (1)
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    Summary form only given: The explosion of the digital consumer electronic market has been also sustained by the availability of successful Non-Volatile semiconductor Memory (NVM) technologies. The key driver has been Flash memory, both in NOR and NAND architecture, which are the preeminent NVM technologies for code and data storage application in portable electronic systems. The needs for higher p... View full abstract»

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  • Mobility enhancement in silicon nanowire transistors

    Publication Year: 2010, Page(s):9 - 12
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (954 KB) | HTML iconHTML

    Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while... View full abstract»

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  • Embedded non-volatile memory circuit design technologies for mobile low-voltage SoC and 3D-IC

    Publication Year: 2010, Page(s):13 - 16
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB) | HTML iconHTML

    Low supply voltage is a commonly method for suppressing system power consumption and thermal effects, improving battery life and chip reliability for mobile SoC and 3D-IC devices. This paper describes various mainstream and emerging embedded non-volatile memory (eNVM) solutions for mobile SoC and 3D-IC designs. This study also reviews and discusses the key circuit technologies for decreasing the V... View full abstract»

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  • Wafer-level magnetotransport measurement of advanced transistors - making a powerful technique even more powerful

    Publication Year: 2010, Page(s):17 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB) | HTML iconHTML

    For transistor research and development, one of the important figures of merit is the carrier mobility. The measurement of mobility is cumbersome in large devices, and nearly impossible in nano scale devices. Very often, effective mobility (μeff) is extracted from the I-V curve instead. There are many pitfalls in equating μeff to mobility (μ), including c... View full abstract»

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  • Future of Nanoelectronics at the end of the roadmap and beyond

    Publication Year: 2010, Page(s):21 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1869 KB) | HTML iconHTML

    The review addresses the major challenges that Nanoelectronics will have to face in the next decades. A multifaced strategy is followed to scale down CMOS based technology with new materials and disruptive architectures, heterogeneous integration, alternatives to MOSFET for information processing introducing 3D schemes at the Front End and back end levels. View full abstract»

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  • Low-voltage memory-rich nanoscale CMOS LSIs -current status and future trends-

    Publication Year: 2010, Page(s):25 - 28
    Cited by:  Papers (1)
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    The minimum operating voltage, Vmin, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using a timing margin is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the threshold-voltage variations, ΔVt, which become more significant with device scaling, and to the lowest necessa... View full abstract»

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  • Silicon photonics technologies for monolithic electronic-photonic integrated circuit applications

    Publication Year: 2010, Page(s):29 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB) | HTML iconHTML

    To overcome the severe information latency and power consumption, and enable significant parallelism based on a radically new communication landscape, instead of the conventional Cu-interconnect, will be a remarkable breakthrough. Converging electronic and photonic integrated circuits (EPIC) on a single chip platform to enable functional diversification emerges as one promising approach which coul... View full abstract»

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  • A holistic methodology to address leading edge FPGA manufacturing challenge

    Publication Year: 2010, Page(s):33 - 36
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    A yield ramp methodology for Field-Programmable Gate Array (FPGA) in advanced technologies has been presented. By optimizing design based defect inspection setups, we can use defect-to-bit overlay mapping method more effectively and more reliably in product failure debug. This is complimentary to the manufacturing fab's test vehicles, electrical tests and physical failure analysis for faster wafer... View full abstract»

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  • Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

    Publication Year: 2010, Page(s):37 - 40
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (585 KB) | HTML iconHTML

    We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μ... View full abstract»

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  • Integration of metallic source/drain (MSD) contacts in nanoscaled CMOS technology

    Publication Year: 2010, Page(s):41 - 45
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    An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barr... View full abstract»

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  • Gigabit CMOS current-mode optical receivers for high-speed digital interface applications

    Publication Year: 2010, Page(s):46 - 49
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    This paper introduces a number of current-mode input configurations for gigabit CMOS optical receivers, including common-gate, regulated-cascode (RGC), current-mirror, etc. Unlike conventional voltage-mode input configurations, the current-mode designs effectively isolate the large input parasitic capacitance from the determination of the bandwidth, hence achieving wide bandwidth for comparable tr... View full abstract»

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  • Advanced non-Si channel CMOS technologies on Si platform

    Publication Year: 2010, Page(s):50 - 53
    Cited by:  Papers (1)
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    CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performance and low power advanced LSIs in the future. In addition, the heterogeneous integration of these materials on the Si platform can provide a variety of applications from high speed logic CMOS to versatile SoC chips, where various functional devices can be co-integrated. In this pr... View full abstract»

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  • Electrostatic discharge (ESD) testing of semiconductor chips and systems - paradigm shifts, and semiconductor industry consequences

    Publication Year: 2010, Page(s):54 - 57
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB) | HTML iconHTML

    Dramatic changes and paradigm shifts are presently occurring in the area of electrostatic discharge (ESD) testing of semiconductor chips and systems which may have significant influence on the semiconductor industry. New semiconductor chip tests that have traditionally been regarded as system level events are now being proposed as requirements on semiconductor chips. As these changes are occurring... View full abstract»

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  • Advanced technology for FPGAs

    Publication Year: 2010, Page(s):58 - 61
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (658 KB) | HTML iconHTML

    Power management and high speed transceiver I/O demands are two major challenges for advanced field programmable gate array (FPGA) at 28nm node. To meet requirements, not only innovations in process technology but also co-optimization of process, circuit and system architecture are required. Advanced process technologies, such as high-k metal gate (HKMG) and enhanced strain engineering, significan... View full abstract»

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  • Outlook for 15nm CMOS research technologies

    Publication Year: 2010, Page(s):62 - 65
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (949 KB) | HTML iconHTML

    So far the most aggressive manufacturing forecast for 22nm technology node is in late 2011, and there still remains many arguments for its next generation, 15nm manufacturing technologies. The major obstacles in front of the manufacturing are (1) high cost fine patterning technology, (2) tradeoff of SRAM cell size and performance, (3) increasing variability, (4) short channel effect control, etc. ... View full abstract»

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