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Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on

Date 12-14 Aug. 1990

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Displaying Results 1 - 25 of 308
  • Proceedings of the 33rd Midwest Symposium on Circuits and Systems (Cat. No.90CH2819-1)

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  • A knowledge engineering tool for load forecasting

    Page(s): 144 - 147 vol.1
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    A description is given of a knowledge engineering tool for short-term load forecasting to be used as an aid in operation and planning of a distribution system. This engineering tool is composed of two parts. First, an artificial neural network is trained to produce the first evaluation of a forecasted load. Then, a fuzzy expert system manipulates actual and forecasted values of real power and weather conditions to find the final forecasted load. Illustrative examples are presented using Hydro-Quebec Power System data.<> View full abstract»

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  • FIESTA II-A PC filter educational synthesis teaching-aid

    Page(s): 504 - 507 vol.1
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    This work deals with FIESTA II, the second version of the continuous-time filter design program FIESTA, and its use as a teaching tool. The user friendly features of the program (highly interactive and graphics capabilities that allow student insight into the approximation and synthesis of active filters) have been extended to include the synthesis of new transconductance-capacitance filter structures, automatic scaling for optimum dynamic range of cascade filter structures, and tolerance analysis, etc. Examples are presented View full abstract»

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  • Symbolic approximation of analog circuits using Sspice

    Page(s): 508 - 511 vol.1
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    Sspice is a symbolic SPICE circuit analyzer and approximator. Input files are in the SPICE format and the program performs a symbolic AC analysis. Symbolic approximation is performed by using the magnitude of the largest term for each power of the Laplace variable s times a user specified threshold View full abstract»

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  • An advanced associative comparator integrated circuit

    Page(s): 641 - 644 vol.2
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    An area-efficient high-performance associative comparator has been developed using standard and custom cells. Although a conservative fabrication technology was used, the throughput of the programmable window comparator (PWC) array exceeds the equivalent of 3×109 8-bit arithmetic operations/second. The architecture can be directly scaled to implement larger associative comparators and significant performance improvements are achievable with advanced CMOS or BICMOS fabrication technologies View full abstract»

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  • Structured analysis for neural networks using Petri nets

    Page(s): 770 - 773 vol.2
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    A neural Petri net model examining the dynamic and parallel activities of the neurons is presented. The structural and behavioral properties of the neuron can be studied in some detail using Petri nets. The advantage of this model over the ones in the current literature is that, it uses less parameters, hence it reduces the overall computation complexity of the model. Examples are given illustrating the way in which the neural Petri net can be employed to simulate the behavior of the neuron View full abstract»

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  • An expert system for digital filter design

    Page(s): 997 - 1000 vol.2
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    The objective of this research is to consider the feasibility of an expert system for designing digital filters. The prototype model serves as the foundation for an expert system capable of deriving a set of transfer function coefficients from a set of points that are sketched by the user. In this expert model, the user specifies a design by sketching (using a mouse) a curve which approximates the desired magnitude plot. The expert system then operates on the set of points which define the curve to determine the design parameters, compute the transfer function, and finally produce a magnitude plot. The current filter possibilities are designed as cascaded second-order section with real coefficients. The authors describe the characteristics of this expert system and focus on the techniques used for implementation and knowledge representation. A design example is included View full abstract»

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  • A memory controller for mapping an array of circular buffers into a RAM

    Page(s): 645 - 648 vol.2
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    A 1.5-μm CMOS ASIC with a total complexity of over 22000 gates has been developed to generate and keep track of the offsets within 32 circular buffers. It offers a fair arbitration of interleaved read/write operations at a maximum data transfer rate of 20 MHz. Although the device is intended for a specialized electronic warfare system application, the design features incorporated make it generic and suitable for other applications such as communications interfaces in multiprocessor systems View full abstract»

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  • Concurrent estimation of signal parameters using extended rational function model

    Page(s): 535 - 538 vol.1
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    A frequency domain based parallel processing scheme for fast estimation of signal parameters from noisy signals is presented. In this scheme, the entire DFT (discrete Fourier transform) based spectrum is divided into several segments. The samples of the transfer function within different segments are modeled independently as rational function models so that they can be processed concurrently in a multiprocessing environment. In this investigation, this new signal parameter estimation scheme was implemented on an Intel iPSC/2 hypercube. Results of this new method are compared with a conventional frequency domain estimation method View full abstract»

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  • An artificial intelligence approach to the behavioral modeling of asynchronous sequential logic circuits

    Page(s): 1115 - 1118 vol.2
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    A method has been developed which uses artificial intelligence techniques to model the functional behaviour of asynchronous sequential logic circuits (ASLCs). It provides a highly structured, interactive approach. The domain representation, production rules, and control strategy are described. The behavioural descriptor of the ASLC design automation system generates a primitive flow table which captures the ASLC's functional behaviour. This methodology has been implemented in the C programming language and currently resides on Sun workstations. This ASLC design automation system has been validated using numerous representative examples and has been found to be much quicker and more reliable than more traditional methods for designing ASLCs View full abstract»

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  • A crosstalk tolerant latch circuit design

    Page(s): 653 - 656 vol.2
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    A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range of or even higher than ±Vdd, becoming under specific conditions a dynamic latch preserving the system from the propagation of unknown quality information. The circuit and the design rules presented are oriented to VLSI circuits design in which crosstalk perturbations may be foreseen View full abstract»

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  • Implementation of expert systems with a relational database manager [power system application]

    Page(s): 985 - 988 vol.2
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    A description is presented of how to use a query-by-example (QBE) relational database manager as a tool for setting up expert systems. The traditional components of an expert system, namely, the knowledge base, the inference engine, and the user interface are structured and integrated into a database environment using the built-in facilities of the database manager. A fault diagnosis expert system for an electric power system is implemented in this environment. The expert system accesses existing databases through database management system query commands View full abstract»

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  • Typical applications of new generation spreadsheets to power system problems

    Page(s): 159 - 162 vol.1
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    This work presents advanced applications of a popular new generation spreadsheet, Lotus 1-2-3 (Release 2 or higher), to core power system problems developed in the context of the Power Engineering Curriculum at the University of Calgary. Specifically, the authors describe application programs using the built-in spreadsheet functions, macro commands, and the Lotus Command Language (LCL), for the formulation of bus admittance and bus impedance matrices for power networks followed by DC and AC load flows and fault calculations. Provision is made for line switching, node elimination, and network reduction in the spreadsheet application programs. Because of the integrated availability of three environments, the visible spreadsheet environment, the macro environment and the LCL environment, new generation spreadsheets like Lotus hold considerable promise as effective teaching, training, or prototyping tools for use by universities as well as power utilities View full abstract»

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  • Computer networks reliability evaluations and intermittent faults

    Page(s): 327 - 330 vol.1
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    The reliability of systems is evaluated on the basis of faults which are permanent in nature, but in reality system failures are also due to faults which are intermittent in nature. Intermittent fault describes a fault or an error that is occasionally present due to unstable hardware or software states. When the system is subject to intermittent and permanent faults, a model for studying reliability of digital systems is set up which is based on a Markov model containing three states View full abstract»

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  • An efficient design method for optimal MOS integrated circuit switched-capacitor LDI ladder filters

    Page(s): 956 - 959 vol.2
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    An optimization-based technique is presented for the design of SC-ladder filters derived from lossless discrete integrator (LDI) structures. LDI SC filters have a number of attractive features, including low sensitivity and ready availability of prototype design data, but suffer from certain errors of approximation inherent in their realization. Capacitance spread can become large in dealing with these errors by conventional methods, and this is then a serious difficulty when integrated circuit realization is attempted. The present design technique eliminates this problem via numerical optimization. The procedure also allows the designer to compensate for the effect of the non-ideal characteristics of practical MOS components including finite gain-bandwidth in the op amps. The technique allows for the use of relatively low sampling frequencies and results in a low-sensitivity filter having an exact frequency response and featuring very low on-chip capacitance spread View full abstract»

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  • The design and comparison of elliptic filters with an OTA-C structure

    Page(s): 484 - 487 vol.1
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    A CMOS operational transconductance amplifier and capacitor (OTA=C) integrator which is used for high-frequency operation has been designed and simulated by the SPICE 2G program. The authors have realized the continuous-time OTA=C elliptic low-pass filters by a cascade method and a signal flow graph (SFG) method using only capacitors and OTAs. The frequency characteristics of the OTA=C filters are compared View full abstract»

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  • A novel technique for computer-aided design of low noise microwave amplifiers

    Page(s): 605 - 608 vol.1
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    A description is presented of a new CAD technique for microwave low-noise amplifiers. It is based on a preliminary analysis procedure that, starting from the knowledge of the noise and scattering parameters of the chosen active device, allows the designer to determine the best compromise among transducer gain, noise figure, and input VSWR. Design is carried out providing separate independent equalizer synthesis whose goal functions are consistent with the selected specifications View full abstract»

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  • Colour identification and quality inspection system for agricultural produce

    Page(s): 657 - 660 vol.2
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    A system has been developed in which color detection is one aspect of an overall quality inspection process. In a typical application, the system can sort and route tomatoes to five output grades according to their ripeness and size. A CCD color television camera inspects the produce passing on a conveyor or rotating rollers. Color quality in an early prototype was determined by matrixing and digitization followed by a two-dimensional lookup table process. The two-dimensional lookup table has now been replaced by a three-dimensional lookup table which can be used to define 262132 or 218 unique colors View full abstract»

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  • An adaptive phase compensation technique for integrable gyrators

    Page(s): 492 - 495 vol.1
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    A new technique for providing stable, high quality factor Y-gyrators over a wide frequency range is presented. A compensating phase shift that tracks the gyrator's parasitic phase shift is adopted using voltage variable capacitors. The technique has been implemented in an ordinary semi-floating gyrator circuit where the useable frequency range was extended from 60 kHz to 220 kHz. Further, the low frequency Q-factor has been seen to be enchanged View full abstract»

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  • A microprocessor platform for a generic protection system

    Page(s): 377 - 380 vol.1
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    An investigation is made of a particular microprocessor board arrangement which serves as the base for a variety of power system protection devices. It calculates the first 15 harmonic components of up to 9 nominal power frequency inputs and updates these harmonics every 2 ms. It dynamically tracks the fundamental frequency and alters the sampling rate to remain at 32 per fundamental cycle. The harmonic components are available for use in a variety of protection algorithms and typical examples are given View full abstract»

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  • Artificial intelligence and concept of step wise fault detection

    Page(s): 1190 - 1193 vol.2
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    A study is made of the concept of artificial intelligence and it is applied to the problem of fault diagnosis to a system which has been designed for t0 fault diagnosis without repair on the basis of a PMC model. The author modifies the connection assignments of each unit of the system in such a way that after t0 units in the system, the nonfaulty units of the system can diagnose t1 additional faults where t1 ⩽[t0/2], and after t1 faults the remaining nonfaulty units can diagnose t2 additional faults where t2⩽[t1 /2], and so on. The process of additional fault diagnosis in a step-wise manner will function, and the process will stop when necessary and sufficient conditions for fault diagnosis are violated View full abstract»

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  • Knowledge based extension of DIADES system for the analysis and synthesis of TGC circuits

    Page(s): 989 - 992 vol.2
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    A new and uniform approach to the computer-aided analysis and synthesis of analog circuits is presented. The system is specialized for transconductance-grounded capacitance circuits (TGC). The analysis is a transformation from a signal flow graph (SFG) to a transfer function (TF). It is based on a step-by-step transformation from SFG to TF by reductions of nodes: summation, multiplication, and feedback. Symbol manipulation of multivariate rational functions is used. The synthesis is a process of transforming a LC-ladder filter SFG to a TGC circuit. Heuristic synthesis procedures, inverse to the ones used in the analysis, search the solution space of equivalent SFGs and are theoretically able to find the optimal solution. The synthesis method includes three stages: SFG labeling, synthesis of the SFG branch transfer functions, and SFG repolarization. The application of some synthesis rules is illustrated on examples View full abstract»

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  • Model reference adaptive control algorithm on a second order dynamic model

    Page(s): 1179 - 1182 vol.2
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    Demonstrates the implementation of model reference adaptive control (MRAC) systems on a linear second-order dynamic model. Two basic structures of MRAC systems are used: the parallel-parallel and the series-parallel systems. Both systems are used for adaptation and estimation, where the parameters of the dynamic model are tuned, to maintain stability, and drive the model's performance to a required criterion. A technique for the selection of adaptation gains is developed. The generality of this demonstration keeps such an approach applicable to any dynamic model simplified to a second-order system View full abstract»

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  • Model reference estimation and control of tool chatter

    Page(s): 681 - 684 vol.2
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    A mathematical model is derived to predict tool chatter in milling processes. The mathematical model parameters are estimated under changing machining conditions by an online model reference series-parallel estimation strategy. By applying the proposed method, variations in the machining process are compensated for by subsequent changes in both the feed velocity and the spindle speed. Changes of feed velocity and spindle speed are carried out by a model reference parallel-parallel adaptive control strategy. The spindle speed and feed velocity are modified to minimize tool chatter and maintain the stability of the whole system. The strategy of estimation and adaptation has been implemented on a computer-controlled milling machine View full abstract»

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  • A fast multiplier design using signed-digit numbers and 3-valued logic

    Page(s): 881 - 884 vol.2
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    A multiplier design using 3-valued (ternary) logic and redundant binary signed-digit (RBSD) numbers is presented. The use of 3-valued logic offers the advantage of reduced circuit complexity in terms of both transistor count and interconnections since each ternary bit can support one digit of the RBSD number system. The choice of a RBSD number system enhances the speed of multiplication by allowing carry-free addition of partial products. While the internal multiplication uses RBSD numbers, both the input operands and the output product are assumed to be in the standard two's complement form. MAGIC and SPICE software tools were used to produce VLSI design layouts and circuit simulation results View full abstract»

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