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Computing Systems (WSCAD-SCC), 2010 11th Symposium on

Date 27-30 Oct. 2010

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Displaying Results 1 - 25 of 34
  • [Front cover]

    Publication Year: 2010, Page(s): C1
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  • [Title page i]

    Publication Year: 2010, Page(s): i
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  • [Title page iii]

    Publication Year: 2010, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2010, Page(s): iv
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  • Table of contents

    Publication Year: 2010, Page(s):v - vii
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  • Conference Organization

    Publication Year: 2010, Page(s): vii
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  • Message from General Chairs

    Publication Year: 2010, Page(s): viii
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  • Mensagem dos Coordenadores Gerais

    Publication Year: 2010, Page(s): ix
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  • Message from Program Chairs

    Publication Year: 2010, Page(s): x
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  • Mensagem dos Coordenadores do Comitê de Programa

    Publication Year: 2010, Page(s): xi
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  • Program Committee and Reviewers

    Publication Year: 2010, Page(s):xii - xiii
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  • Brazilian Computer Society

    Publication Year: 2010, Page(s):xiv - xvi
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  • Parallel Routing Algorithm for Extra Level Omega Networks on Reconfigurable Systems

    Publication Year: 2010, Page(s):1 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (403 KB)

    Several parallel routing algorithms have been proposed during the last three decades. However, most algorithms have been not implemented. Therefore, the execution time and memory resources have been neither measured nor reported. This work presents two parallel routing algorithms for Omega multistage networks by using hardware assistant approach. Both algorithms have been mapped on a FPGA. The fir... View full abstract»

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  • A Proposal of Parallelization of Local Search Procedures Applied to the Minimum Cost Hop-and-Root Constrained Forest Problem

    Publication Year: 2010, Page(s):9 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    In this work, we present two parallel heuristics that coordinate the application of many local search procedures to the Minimum Cost Hop-and-root Constrained Forest Problem (MCHCFP), a Combinatorial Optimization problem in which the minimization of the communication costs in a wireless sensor network with constrained delay and number of hops is desired. The coordinated application of local search ... View full abstract»

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  • Simulation of the Foreground-Background Queue in Parallel Systems

    Publication Year: 2010, Page(s):17 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB) | HTML iconHTML

    This paper presents a simulation study of the FB scheduling policy in the presence of system loads of varying intensity and variability. The FB policy is compared with the policies FCFS, PS and SRPT, under the same conditions, in mono and multiprocessor environments. The results show that the policy FB is very appropriate for extreme situations, in which there is large variability in service time ... View full abstract»

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  • Influence of Communication Models on the Scalability of Master-Slave Platforms Running Bag-of-Tasks Applications

    Publication Year: 2010, Page(s):25 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB) | HTML iconHTML

    Bag-of-Tasks applications are parallel applications composed of independent (i.e., embarrassingly parallel) tasks that do not communicate with each other, may depend upon one or more input files, and can be executed in any order. Each file may be input for more than one task. A common framework to execute BoT applications is the master-slave topology. In this paper we studied the scalability of Bo... View full abstract»

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  • Optimizing a Retargetable Compiled Simulator to Achieve Near-Native Performance

    Publication Year: 2010, Page(s):33 - 39
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (514 KB) | HTML iconHTML

    The design of new architectures can be simplified with the use of retargetable instruction set simulation tools, which can validate the decisions in the design exploration cycle with high flexibility and reduced cost. The increasing system complexity makes the traditional approach to simulation inefficient for today's architectures. The compiled simulation technique makes use of a priori knowledge... View full abstract»

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  • Advanced SS: A Superscalar Simulator with Support for Operating System

    Publication Year: 2010, Page(s):40 - 47
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (327 KB) | HTML iconHTML

    Computer simulation has allowed the analysis of behavior and performance of systems still in its design phase. The Advanced Superscalar Simulator project is a tool for simulation of a complete computer system, involving the simulation of a superscalar processor and an input and output system, with infrastructure for symmetric multiprocessing. It can also run an operating system in the simulated ha... View full abstract»

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  • Hardware Accelerator for Dictionary-Based Compression of MMP Algorithm

    Publication Year: 2010, Page(s):48 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (443 KB) | HTML iconHTML

    The MMP is an algorithm for image compression which uses the multiscale method of recurrent patterns, based on dictionary. The MMP has compression ratio at the same level of others compression algorithms which are based on transforms, having been detached to images with high frequency, however its execution time has been shown high, by repeated searches of these patterns in dictionaries. In this p... View full abstract»

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  • D-Power: A VHDL Dynamic Power Estimation Tool for Superscalar Architectures - Cache Hierarchy and Fetch Stage

    Publication Year: 2010, Page(s):56 - 63
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (345 KB) | HTML iconHTML

    Technological innovations constantly emerge in computer systems. Its primary focus is on the improvement of performance. One way to improve performance is to increase the hardware. However, this increase in hardware has its implications, like a larger area required on the chip and a consequent increase in power consumption. This boost in power consumption raises heat dissipation, difficult cooling... View full abstract»

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  • NSGAII Applied to Unified Second Level Cache Memory Hierarchy Tuning Aiming Energy and Performance Optimization

    Publication Year: 2010, Page(s):64 - 71
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (497 KB) | HTML iconHTML

    The evolutionary algorithm NSGAII was applied to the problem of cache memory hierarchy optimization, considering unified second level. The proposed multi-objective approach considers two main objectives: energy consumption and performance related to the number of cycles necessary to run an application. Experiments done with 18 applications from two benchmarks (Power Stone and Mibench) permitted to... View full abstract»

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  • Process Mapping Based on Memory Access Traces

    Publication Year: 2010, Page(s):72 - 79
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (225 KB) | HTML iconHTML

    Process mapping is a technique widely used in parallel machines to provide performance gains by improving the use of resources such as interconnections and cache memory hierarchy. The problem to find the best mapping is considered NP-Hard and, in shared memory environments, there is the additional difficulty to find the communication pattern, which is implicit and occurs through memory accesses. I... View full abstract»

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  • Implementation of Techniques for Fault Tolerance in a Network-on-Chip

    Publication Year: 2010, Page(s):80 - 87
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB) | HTML iconHTML

    Networks-on-Chip (NoCs - Networks-on-Chip) have emerged as the best alternative to provide high performance in communication for futures Systems-on- Chip (SoCs) with dozens of cores integrated on a single silicon die. However, the components of a NoC are susceptible to faults resulting from heating, power surge, external radiation and others. Faults in a router or a network link can lead to the tr... View full abstract»

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  • Scheduling Strategies Evaluation for Opportunistic Grids

    Publication Year: 2010, Page(s):88 - 95
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (170 KB) | HTML iconHTML

    On this work we evaluate scheduling strategies usually applied on heterogeneous distributed environments, taking into consideration the characteristics of opportunistic grids. On the explored scenarios, several parameters are considered and correlated, such as application arrival rate, the occurrence of failures, application tasks size and heterogeneity, and the time to recover from application fa... View full abstract»

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  • A Model to Explore Business Opportunities in Ubiquitous Environments

    Publication Year: 2010, Page(s):96 - 103
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (478 KB) | HTML iconHTML

    The mobile and ubiquitous computing has been stimulated by the widespread diffusion of mobile devices, wireless networks, and, more recently, by location systems. In this context, applications are emerging in different areas, such as, education, entertainment, and commerce. The application of the ubiquitous computing in the exploration of business opportunities is called Ubiquitous Commerce. This ... View full abstract»

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