By Topic

Electronic System-Integration Technology Conference (ESTC), 2010 3rd

Date 13-16 Sept. 2010

Filter Results

Displaying Results 1 - 25 of 223
  • Program

    Page(s): 1 - 69
    Save to Project icon | Request Permissions | PDF file iconPDF (1912 KB)  
    Freely Available from IEEE
  • [Front matter]

    Page(s): 1 - 27
    Save to Project icon | Request Permissions | PDF file iconPDF (2209 KB)  
    Freely Available from IEEE
  • 3D substrate innovation for complex high pin count flip-chip applications

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (645 KB) |  | HTML iconHTML  

    Due to the increased complexity and greatly expanded I/O on today's multiple function semiconductors, IC suppliers have been forced to abandon the traditional wire-bond package assembly, opting instead for the more compact die face-down flip-chip attachment methodology. This face-down, direct attachment method significantly reduces the semiconductors package outline as well as enhancing product performance. While wire-bond interface may remain the preference for many applications, face-down direct chip attachment has gained wide acceptance for the higher-speed processor and ASIC products. The majority of these high pin-count die are being furnished with a very fine-pitch solder bump array contact pattern, many with less than 150 micron pitch. The array pattern on the die element is provided through series of metallization and lithographic processes while the die remain in the wafer level format. This array configured contact pattern enables greater flexibility for die-to-substrate interface routing. Key substrate requirements to be resolved when mounting higher pin count die to a multi-layer glass/epoxy based structure is the ability to overcome irregular solder bump profiles, and the physical affects (warping) of the substrate during high temperature Pb-free soldering. This paper will describe a new raised contact interconnect solution for high-density, multi-layer substrates. The process was specifically developed for mounting very-fine-pitch bumped flip-chip semiconductor die, overcoming both solder bump uniformity concerns and solder process compatibility issues. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thin wafer processing and chip stacking for 3D integration

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (860 KB) |  | HTML iconHTML  

    The advantages as well as the technical feasibility of through silicon vias (TSV) and 3D integration have been widely acknowledged by the industry. Today the major focus is on the manufacturability and on the integration of all the different building blocks for TSVs and 3D Interconnects. In this paper the advances in the field of thin wafer processing and wafer bonding are presented with emphasis on the integration of all these process steps. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Eutectic wafer bonding for 3-D integration

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (895 KB) |  | HTML iconHTML  

    Successful commercialization of MEMS products extremely depends on cost factors. Especially the role of integration technologies like packaging at different levels, combining MEMS with integrated circuits, and to realize 3-dimensional packaged devices is more important than ever. Bonding technologies at wafer level are key factors for 3-d integration, realizing the mechanical bond and fulfilling certain requirements like strength, hermeticity, and reliability as well as the electrical interconnection of the different functional components. From a great variety of bonding techniques eutectic bonding has got a special importance today because both hermetically sealed packages and electrical interconnects could be performed within one bonding process. Furthermore, there are some advantages such as low processing temperature, low resulting stress, and high bonding strength. These properties are mainly investigated up today. Since the early 90-ies eutectic wafer bonding is known from very large scale integration (VLSI) and is used very often in industry. Even before that time eutectic bond processes were already used in the field of chip bonding. Within this paper the development and investigation of at least two eutectic bonding technologies will be described and characterized. Although the mechanical and micro structural properties of the bond will be shown, the realization and test of electrical interconnects is focused very clearly. With an integration of certain test structures the bonding strength, the electrical properties, and the hermeticity of eutectic bonds could be measured and evaluated. At least it will be concluded with an outlook for the feasibility of eutectic bonding in 3-d integrated smart micro systems. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wafer-to-wafer hybrid bonding technology for 3D IC

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1408 KB) |  | HTML iconHTML  

    In this research, the wafer-level metal/adhesive hybrid bonding technology was developed to perform the 3D integration platform. Four kinds of polymer materials, BCB, SU-8, AL-Polymer, and PI, were evaluated as the bonding adhesive for hybrid collocation with metal. After realizing the bonding properties, the qualified ones were patterned on wafers, and sequentially bonded by metal bonding conditions. Two kinds of conditions were simulated, one is Cu-Sn eutectic bonding, and the other is Cu-Cu thermo-compression bonding. The compatibility between each polymer and metal was evaluated, and the application range of each material was established thereof. Furthermore, samples with hybrid scheme were fabricated to perform hybrid bonding and realize the compatibility in whole process. The micro-bump/Cu-pad size less than 20μm and thickness less than 5μm were designed for interconnection. The bonding quality and interface investigation on metal/adhesive were analyzed to make sure the interconnection and micro-gap filling between stacked wafers. The evaluation results of wafer-level hybrid bonding and material candidates will be disclosed in the paper. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Stacked Anodized Metal Substrate for high thermal dissipation performance

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1106 KB) |  | HTML iconHTML  

    A novel fabrication method for stacking metal substrates using AMS (Anodized Metal Substrate) is suggested. This stacking technology can meet needs about superior heat dissipation capabilities for multi layer substrate in some application fields like automobile electronics applications. Moreover conventional processes which have been used for normal PCB (Printed Circuit Board) process and any special processes are not adopted for it. Therefore stacked structure over 4 layers using AMS can be realized by low cost. The realized stacked substrate is applied to automobile ISM (Image Sensor Module). The maximum temperature difference between surface of the hottest point of AMS and organic PCB reach about 10 °C. Through decrease of temperature of the hottest part, various components on the substrate can be protected from excessive heat. Therefore reliability and performance of module can be improved drastically. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reliability improvements for advanced Wafer Level packaging

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2875 KB) |  | HTML iconHTML  

    Over ten years ago, Wafer Level Chip Scale Packaging (WLCSP) began with very small packages having solderball counts of 2-6 I/O. Over the years, the I/O count has grown, but the industry perception has always been that WLCSPs are limited to low I/O count applications. Within the last year, there has been a growing demand for WLCSP packages with I/O counts greater than 150, with some applications requiring I/O's of more than 300. As each generation of WLCSP has grown in complexity, it has strained the capabilities of the processes, material sets, and structures that performed satisfactorily in previous generations. It has been observed that while manufacturing WLCSP products for a wide variety of customers, as we go above 100 I/O, and then again above 150 I/O, the structural and compositional parameters of the WLCSP have had to be modified in order to pass the end customer's reliability requirements. This paper will explore the impact of material, process, and structural variations to a large scale WLCSP, on Board Level Reliability. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wire-bonding on inkjet-printed silver pads reinforced by electroless plating for chip on flexible board packages

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1809 KB) |  | HTML iconHTML  

    The nanoporous nature of the inkjet printed silver nanoparticles entail low hardness and surface effective contact area for being compatible with pads that are suitable for wire-bonding in electronic packaging. Electroless nickel plating is a selective metal deposition technique which can brings the required thickness and hardness for further pads processing. Here, a 1.7 μm thick nickel layer is deposited on top of 600 nm thick printed and sintered silver nanoparticles using Kapton polyimide as substrate. Prior to plating, a special attention was put on tuning microstructures of printed silver pads by sintering nanoparticles at various temperature ramps (0.1, 10 and 50°C/s) up to 200°C. Results show that fast sintering exhibits the lowest electrical resistivity which is suitable in printed interconnects. However, wire-bonding on nickel pads is best achieved when low sintering ramp is used. This slow sintering presents the highest adhesion strength at the nickel/silver interface since the pores dimensions were restricted to the nanoscale. The validation of the optimized bonding process came from the low electrical contact resistance between plated nickel and the bonded gold wire, and from the wire-pull test which is in accordance with the MIL-STD 883 standard. The actual results show that a compromise has to be found when emphasis is on patterning low resistive interconnects or stiff pads for wire-bonding applications. This compromise is tailored by the sintering engineering. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low profile CSP (LP-CSP) technology for ultra-thin IC packaging applications

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (943 KB) |  | HTML iconHTML  

    Miniaturization of mobile electronics and consumer devices has resulted in a three dimensional (3D) scaling trend for Wafer Level Chip Scale Packaging (WLCSP) technology. Horizontal scaling and the impact on device reliability have been described in detail in many previous publications. Horizontal scaling typically implies reduction in the I/O pitch leading to a smaller die size. The device reliability measured with respect to temperature-cycling tests and drop tests, improves as the I/O pitch reduces. Scaling rules have been developed for horizontal scaling. In this paper, we discuss the vertical scaling of WLCSP technology that does not follow conventional scaling rules. Aggressive scaling is implemented in the vertical dimension to arrive at a low form factor package technology. Such a packaging technology is extremely useful in space constrained, ultra-thin, consumer electronics products. We discuss the fabrication technology and then present the reliability results. A simple RC filter circuit is used as a test vehicle to compare the performance and reliability of the new LP-CSP process with the conventional CSP process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hermetic wafer-level packaging development for RF MEMS switch

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1566 KB) |  | HTML iconHTML  

    This paper presents a low temperature (<;;350°C) hermetic solution to fully package at wafer level a RF MEMS switch connecting upwards. The switch has a piezoelectric actuation and an electrostatic hold. In this architecture, the packaging is actually part of the switch itself and shall meet many requirements: 1. Use of Thru-Silicon Via (TSV) for DC and RF connections with minimum via resistance 2. Electrical connection between both wafers 3. Hermetic sealing under controlled atmosphere with 5+/-0.5 μm gap between the switch and the cap wafers 4. No degradation of the switch performances 5. Low temperature (<;;350°C) packaging process to preserve the moving part materials 6. Electrode and dielectric for electrostatic hold 7. No sticking of the moving contact Two main processes were developed and implemented together: Au-Sn eutectic bonding under atmospheric pressure with 5μm spacers to ensure the gap, and 'post-bonding' TSV. The complete process flow of the cap wafer, bonding and TSV process is presented. The solder material, made of 80wt.%Au and 20wt.%Sn, is only 5μm thick and is electroplated. SEM, XPS, EDX analyses and shear tests have been performed. Hermeticity evaluation tests have been set-up, and a standard leak rate lower than 1.2 × 10-12 mbar.1/s has been demonstrated using the membrane deflexion method. TSV and Au-Sn bump resistance is less than 14mΩ and lOmΩ with a yield of 92% and 98% respectively across the 200mm wafer. The resistance between 2 via is more than 500MΩ at 5V. As to the packaged switch, its insertion losses at 2 GHz are 0.74dB and its off-state isolation is 43.6dB. At last, it has been demonstrated that the substrates resistivity has a great influence on the insertion losses. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Module miniaturization by ultra thin package stacking

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1073 KB) |  | HTML iconHTML  

    The scope of the European project TIPS (Thin Interconnected Package Stacks) is the fabrication of ultra thin packages for electronic components and the subsequent stacking and interconnection of those packages to form highly compact modules. In the first part of this paper approaches to fabricate ultra thin 10 × 10 mm packages by embedding technologies for chips into printed circuit board environments will be discussed. One technology uses commercial flexible printed circuit board substrates (polyimide sandwiched in Cu layers) and respective fabrication processes. After initial patterning of the Cu the chips are die bonded to the flex substrates and subsequently laminated into build up layers. Electrical contact between the chip and a fan out routing on the outer layer of the package are made by micro via formation, electroplating and wet chemical structuring of the metal layers. The thickness of the embedded components is constricted to 50 μm in order to constrain the package thicknesses to a maximum of 100 μm with this approach. The alternative approach, the ultra thin chip package (UTCP) technology, aims at package thicknesses around 60 μm. In this case 20 μm thick chips are die-bonded to thin polyimide layer. A photo-definable polyimide is then applied over the assembled chips by spin-on technique. Contact pads are opened by exposure and development of the polyimide, followed by metal sputtering, electroplating and etching. In this approach the thickness of embedded components is typically 20-30 μm and final package thickness is in the range of 60 μm. In both approaches the packages are fabricated as batches consisting of 150 × 150 mm sheets of flex substrates. Stacking of individual packages can be performed in an automated package by package placement process using a frame as alignment tool and typical flexible printed circuit boards adhesives. In this way only known-good-packages are stacked in o- - rder to minimize yield loss. However, a more straight forward process is stacking of the packages using fabrication batches and established multilayer printed circuit board technologies. The disadvantage is the potential yield loss if one of the packages in a stacked layer is faulty. For either type of stacking process the individual stacks have to be milled out of the stack fabrication batch. Development issues, design considerations and results of first fabrication runs will be presented and discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implementation of chip embedding processes for the creation of miniaturized system-in-packages

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1826 KB) |  | HTML iconHTML  

    This paper details the newest developments in chip embedding technologies for chips with a pitch of 100μm. The technology developed in this study does not necessitate expensive redistribution layers for enlarging the pad pitch. Embedding of small pitch chips has been realised with concurrent developments in accurate chip positioning, plating methods and chemistries and ultra fine line patterning. The results in this paper show the emergence of a new prototype Embedded chip-QFN package with contact pads at 400μm pitch and a total number of 84I/Os with dimensions of 10mm×10mm. The embedded chip in the QFN package is 5mm×5mm in size and has a peripheral pad configuration at 100μm pitch. All Embedded chip-QFN packages have been manufactured in 10"×14" panels at prototype level. This paper also presents developments in semi-additive processing up to 15μm L/S copper structuring on very thin copper foils. Package reliability studies have shown excellent resin/chip adhesion and good thermo-mechanical stability of embedded interfaces for all tests. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integration of a 3D microwave module

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1098 KB) |  | HTML iconHTML  

    With respect to a planar approach, 3D stacking of functional layers allows to increase the level of integration and miniaturization of communications systems. For this paper, a full 3D stacking demonstration vehicle has been realized and characterized. The feasibility of a 3D micro-wave module package has been proven by the successful realization of a 30 GHz 3D module including substrate vias, low loss interconnects, substrate shielding and MMIC integration. The impact of wire bond and CAP integration on 3D packaging performance were also investigated. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (513 KB) |  | HTML iconHTML  

    In this work, two different reliability experiments, thermal cycling and electromigration, are performed on fully packaged Si-to-Si stacks bonded with Cu-Sn intermetallic (IMC) micro-bumps. These experiments investigate both the more critical thermo-mechanical behavior as well as the expected positive thermal-electrical behavior. The Cu-Sn IMC bumps survive thermal cycling for more than 3900 cycles between -40 and 125°C with 1 hour per cycle. The resistance to electromigration is strongly dependant on the used Sn thickness and shows an improved performance for thinner Sn samples (3.5μm) compared to thicker Sn (8μm). In either case, IMC bumps outperform standard solder flip chip bumps. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • TSV as an alternative to wire bonding for a wireless industrial product: another step towards 3D integration

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1128 KB) |  | HTML iconHTML  

    3D integration development has to be driven by industrial demand and applications. To get interested in those technological developments, industrials shall be convinced by benefits of Through Silicon Vias (TSV) integration versus traditional assembly approach. This will demonstrate that this approach is worth being more developed and implemented. In this study, we demonstrated that we are able to achieve similar performance for a given product using a standard wire bonding packaging and an integration with TSV. Both electrical measurements on test structures and characterization on product are compared. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Technology trends in the manufacturing and packaging of Wafer Level Cameras

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1272 KB) |  | HTML iconHTML  

    For many years digital cameras have been integrated into mobile phones. In the beginning the camera phone was just another gimmick with limited value to the end user. Today, imaging is considered as a core feature by the user and major mobile phone manufacturers and most mobile phones are equipped with two cameras, a primary Mega-Pixel (MPx1) camera for photography and a secondary CIF or VGA camera for video calls. Far more than a billion mobile phone cameras were sold in 2009, and the numbers are still increasing rapidly. The increasing demand for more functions and features coming along with cost reduction plays a significant role in today's product design and manufacturing technologies of mobile phones and pushes the industry to continuously improve the performance and the manufacturing technologies. Wafer Level Cameras (WLC) is supposed to be the technology of choice to address these requirements. This application currently drives many equipment and process innovations that will become key for cost effective 3D and MEMS packaging later on. Within the manufacturing process of wafer level cameras one can identify two complementary technologies. One is the wafer-level packaging of image sensors and the other is the wafer-level manufacturing of camera objectives. Both the sensor device and the objectives will be finally assembled on wafer level by a wafer bonding process. However, today's reality is the wafer level manufacturing of the optical module and the chip-level assembly of optical module and image sensor chip. Wafer level optics (WLO), part of the wafer-level manufacturing of cameras, is a novel technology that is designed to meet the demand for smaller form factors of the optical system and cost reduction in the next generation of camera phones. The optical components are fabricated by UV replicating the optics through a stamp material into a polymer layer, coated on a glass wafer. Another key challenge in the manufacturing is the alignment in the wafer b- - onding process step. Replicated lens wafers are aligned and adhesively bonded at the wafer level using a UV curing process in order to achieve excellent alignment results. Finally the bonded Opto Wafers are subsequently diced to form individual camera modules. This paper explores the latest fabrication techniques used in the Wafer Level Camera manufacturing process (WLC) to support >3MPxl systems and describes main challenges and available solutions. The paper presents latest lithography results of TSV formation, the replication of micro lenses (Fig. 2) and the wafer level packaging of microlens wafers (Opto Wafers) via UV bonding are depicted as well. Finally new UV curable materials for microlens replication and for Wafer Level Packaging of Opto Wafers (lens stacking) are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3D IC infrastructure status and issues

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB) |  | HTML iconHTML  

    Performance requirements such as increased bandwidth and lower power are driving the adoption of 3D ICs designed with through silicon vias. Many companies and research organizations have described the advantages of stacking chips vertically. There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. As companies move from R&D into production the difficult work begins in addressing the issues of design, thermal management, test, and assembly. Different needs and economic factors determine the timing of adoption in each application. Issues in moving to volume production include the installation and qualification of high-volume 300 mm production lines, assembly and test capability, the availability of TSV interposers, and reliability data. This presentation provides an assessment of the infrastructure for 3D TSV and provides an update on the remaining barriers to adoption. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel approach to embed off-chip RF passives in PCB based on thin film technology

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (462 KB) |  | HTML iconHTML  

    Embedding passive components (EPCs) is known as a promising technology to provide high electrical performance and to reduce fabrication cost. This paper describes a novel approach to embed off-chip RF passives based on thin film stack. Multilayer structures are built-up on temporary glass carrier substrates by repetitive application of spin-coated polyimide layers and sputtered metal layers. After processing and testing the structures can easily be released from the carrier and embedded inside PCB or FCB (flexible PCB). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System integration with eWLB

    Page(s): 1 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2816 KB) |  | HTML iconHTML  

    Fan-Out Wafer Level Packaging has arrived in the industry. The driving factors for the implementation of this packaging technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density on chip side and the potential for Integration of functionality. The increasing demand for new and more advanced electronic products with superior functionality and performance is driving the integration of functionality for future packaging technologies. The best-known representative of the existing fan-out Wafer Level Packaging Technologies is eWLB (embedded Wafer Level Ball Grid Array), which was invented and introduced by Infineon. eWLB is a true wafer level packaging technology starting with the generation of an artificial wafer. This artificial wafer allows the addition of package area leading to free selectable package size and number of interconnect elements at a given pitch. The driving factors for the implementation of this technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density and the potential for integration of functionality. Two major approaches for system integration on basis of the eWLB technology include side-by-side multi-chip approaches and three-dimensional stacking. For the Multi-Chip eWLB Package several chips were placed close to each other and were encapsulated in one package. Warpage improvement and die shift optimization lead to a process ability for the multi-die wafers comparable to the single die eWLB. Reliability testing indicated no special Multi-Chip Package related fails. We will introduce the results of the development of two-die Multi-Chip eWLB and present the actual reliability results. For the three-dimensional stacking two different ways to generate the interconnection in z-direction were investigated: The placement of pre-fabricated via bars prior to the moldi- - ng of the Reconstituted Wafer and the laser drilling and copper filling of vias in the mold compound. Both principles were investigated with regards to the vertical interconnect and the two-sided processing. Reliability testing showed no special package related failure modes. In this paper we will introduce recent results of the development of both connection strategies for 3D-eWLB, show the challenges of the technology development and present actual reliability results. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fan-Out Wafer-Level Packaging with highly flexible design capabilities

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2685 KB) |  | HTML iconHTML  

    We have developed a new Fan-Out Wafer-Level Packaging (FO-WLP) technology with flexible design capabilities for multilayer fan-out redistribution layers (RDLs) connected to the fine-pitch I/O pads of chips. The prototype of a 2.0 mm × 2.0 mm FO-WLP with 25-pin land grid array (LGA) including a 1.6 mm × 1.6 mm microcontroller chip was fabricated and evaluated. Board-level reliability was also confirmed using 5.0 mm × 5.0 mm FO-WLP. This technology is suited for applications in extremely small microcomputer chip/system packaging for ubiquitous computing. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Process integration of fine pitch micro-bumping and Cu redistribution wiring for power efficient SiP

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2165 KB) |  | HTML iconHTML  

    Leading-edge LSI products with 40nm logic technology node and beyond are facing the issue of how higher memory bandwidth is reconciled with lower power consumption. Chip stacking of a logic chip on a large-scale DRAM chip, interconnected with each other by fine-pitch bumps, provides a solution to realize a power efficient SiP (System in Package). In this paper, the successful process integration of 10μm pitch Cu redistribution wiring and 40μm pitch SnCu micro-bumping on 300mm wafers, together with chip-on-chip (CoC) joining, has been described in an effort to relinquish embedded DRAM (eDRAM) SoC (System on Chip). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electron backscatter diffraction microstructure investigations of electronic materials down to the nanoscale

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2279 KB) |  | HTML iconHTML  

    In this paper, the application of electron backscatter diffraction (EBSD) methods to materials used for common microelectronic interconnection technologies is demonstrated with particular emphasis to lead-free soldered interfaces and thermosonic wire bond interconnects. Here, the paper focuses on the quantitative analysis of grain orientation, grain size and grain distribution of SAC as well as gold, aluminum and copper bonding wire materials. In addition special attention is paid to high resolution analysis of the intermetallics formed in the interfaces of microelectronic packaging interconnects. The application and the potential of EBSD to detect the Cu/Sn, Ni/Sn and Au/Al intermetallics being practically relevant for soldering and wire bonding is demonstrated. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Flexible test bench to study the reliability of electronic assemblies

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1462 KB) |  | HTML iconHTML  

    Robustness and reliability for electronic boards are key issues, especially in the aeronautics industry. To study the reliability of the assembly, accelerated tests are performed on daisy chain components assembled on Printed Circuit Board (PCB). Times to failure of components need to be accurately detected to propose relevant fatigue and reliability models. To electrically monitor the daisy chains, a flexible event detector has been developed by EADS Innovation Works. Its aim is to detect micro-events in a solder joint. Indeed, despite the crack initiation and propagation, the solder joint can still conduct electrical current intermittently. Nevertheless, the solder joint is not considered as reliable because it is not able to fulfill its function in any case. Firstly, this paper presents the characteristics of the flexible event detector. A part of the system records continuously micro-events, for a large number of channels. Then, a custom interface analyse the data recorded by the multi channels system to identify those which correspond to standards (such as IPC-SM-785) or a custom criteria. To illustrate this method and validate the event detector, some experimental vibration tests were performed. Several components electrically failed during the tests and were precisely detected by the flexible event detector. Finally, a comparative vibration testing is performed between a commercial event detector system and the EADS IW one to identify the detection capacities of each solution. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • fibDAC stress relief - A novel stress measurement approach with high spatial resolution

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1358 KB) |  | HTML iconHTML  

    fibDAC stress relief is a new method developed to measure stresses on micro and nanotechnology devices. The classical macroscopic technique of stress relief by material removal has been adopted to determine stress with very high spatial resolution and marginal restrictions regarding the material under test. Focused Ion Beam (FIB) milling is used to remove locally material. Cross correlation algorithms on high resolution SEM images captured in the same FIB equipment reveal tiny stress relief deformations. Their analysis allows computation of stresses present at the place of ion milling. Thorough qualification of the approach resulted in a stress measurement accuracy of 1-5·10-4E, where E is the Young's modulus of the material tested. Lateral resolution of stresses can be reduced to a value around 200 ... 500 nm. Although the method needs finite element stress modeling, it is free of basic assumption upon the kind of stress and the stress built-up history. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.