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Architectures for Networking and Communications Systems (ANCS), 2010 ACM/IEEE Symposium on

Date 25-26 Oct. 2010

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  • Start

    Publication Year: 2010 , Page(s): 1
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  • [Front cover]

    Publication Year: 2010 , Page(s): c1
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  • [Copyright notice]

    Publication Year: 2010 , Page(s): 1
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  • Message from the general chair

    Publication Year: 2010 , Page(s): 1 - 2
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  • Table of contents

    Publication Year: 2010 , Page(s): 1 - 3
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  • ANCS 2010 symposium organization

    Publication Year: 2010 , Page(s): 1
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  • Industrial sponsors

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  • Fair multithreading on packet processors for scalable network virtualization

    Publication Year: 2010 , Page(s): 1 - 11
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (467 KB) |  | HTML iconHTML  

    Network virtualization requires careful control of networking resources, including link bandwidth, router memory, and packet processing time. Isolation and fair sharing of processing resources in current high-performance packet processors occur at the granularity of entire processor cores. Scaling of network virtualization to larger numbers of parallel slices requires a more fine-grained processor sharing mechanism. Our work presents a novel approach, called Fair Multithreading (FMT), that allows hardware threads to share a processor core while ensuring isolation and weighted fair access. We present an analysis of the FMT algorithm and a prototype implementation on a NetFPGA system. Our evaluation results indicate that FMT can be implemented at speeds that are necessary to make scheduling decisions at the instruction level. We show the impact of having such fine-grained processor schedulers in substrate nodes by comparing the resource utilization of virtual network slices in our system to traditional whole-core allocations. Our simulation results show the FMT-based substrate networks can be utilized more efficiently and more virtual network requests can be accommodated. These results indicate the significant improvement in system scalability that can be gained from our fine-grained processor scheduling system. View full abstract»

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  • A folded pipeline network processor architecture for 100 Gbit/s networks

    Publication Year: 2010 , Page(s): 1 - 11
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1397 KB) |  | HTML iconHTML  

    Ethernet, although initially conceived as a Local Area Network technology, has been steadily making inroads into access and core networks. This has led to a need for higher link speeds, which are now reaching 100 Gbit/s. Packet processing at this rate represents a significant challenge, that needs to be met efficiently, while minimizing power consumption and chip area. This level of throughput favours a pipelined approach, thus this paper takes a traditional pipeline and breaks it down to mini-pipelines, which can perform coarse-grained processing (like process an MPLS label to completion). These mini-pipelines are then parallelized and used to construct a folded pipeline architecture, which augments the traditional approach by significantly reducing power consumption, a key problem in future routers. The paper compares the two approaches, discusses their advantages and disadvantages and demonstrates by quantitative measures that the folded pipeline architecture is the better solution for 100 Gbit/s processing. View full abstract»

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  • Design of a secure packet processor

    Publication Year: 2010 , Page(s): 1 - 10
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (326 KB) |  | HTML iconHTML  

    Programmability in the data path of routers provides the basis for modern router implementations that can adapt to new functional requirements. This programmability is typically achieved through software-programmable packet processing systems. One key concern with the proliferation of these programmable devices throughout the Internet is the potential impact of software vulnerabilities that can be exploited remotely. We present a design and proof-of-concept implementation of a packet processing system that uses two security techniques to defend against potential attacks: a processing monitor is used to track operations on each processor core to detect attacks at the processing instruction level; an I/O monitor is used to track operations of the router to detect attacks at the protocol level. Our prototype implementation on the NetFPGA system shows that these monitors can be implemented to operate at high data rates and with little additional hardware resources. View full abstract»

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  • Airblue: A system for cross-layer wireless protocol development

    Publication Year: 2010 , Page(s): 1 - 11
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1627 KB) |  | HTML iconHTML  

    Over the past few years, researchers have developed many crosslayer wireless protocols to improve the performance of wireless networks. Experimental evaluations of these protocols have been carried out mostly using software-defined radios, which are typically two to three orders of magnitude slower than commodity hardware. FPGA-based platforms provide much better speeds but are quite difficult to modify because of the way high-speed designs are typically implemented. Experimenting with cross-layer protocols requires a flexible way to convey information beyond the data itself from lower to higher layers, and a way for higher layers to configure lower layers dynamically and within some latency bounds. One also needs to be able to modify a layer's processing pipeline without triggering a cascade of changes. We have developed Airblue, an FPGA-based software radio platform, that has all these properties and runs at speeds comparable to commodity hardware. We discuss the design philosophy underlying Airblue that makes it relatively easy to modify it, and present early experimental results. View full abstract»

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  • An architecture for Software Defined Cognitive Radio

    Publication Year: 2010 , Page(s): 1 - 12
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1915 KB) |  | HTML iconHTML  

    As we move forward towards the next generation of wireless protocols, the push for a better radio physical layer is ever increasing. Conventional radio architectures are limited to narrow operating regions and fails to adapt with changing technology. This is further strengthened with the advent of cognitive radio, which needs a more versatile and flexible framework that is programmable within the timing constraints of a protocol. In this paper we present an architecture for Software Defined Cognitive Radio that caters to the specific baseband processing requirements in a changing environment. We aim to provide more flexibility by de-constructing the radio pipeline into a framework of user controlled kernels that can be reconfigured at run-time. This architecture provides the barebones of a OFDM based radio physical layer that can adapt to perform a varied number of tasks in different radio networks. We also present a novel message based real-time reconfiguration method to transmit and receive a wide range of waveforms used in concurrent wireless protocols. View full abstract»

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  • End-to-end congestion management for non-blocking multi-stage switching fabrics

    Publication Year: 2010 , Page(s): 1 - 2
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (104 KB) |  | HTML iconHTML  

    In Fig. 3, we depict the average delay of packets targeting non-hotspots, for various numbers of hotspots, each over-loaded by 2.5×, under bursty arrivals, with average burst size of 36. Each request or grant may refer to up to 128 segments in a virtual-output-queue (VOQ), thus reducing control overhead. The switching fabric assumed here is a 64×64, three-stage Clos, made of CIOQ switching chips. View full abstract»

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  • High speed pattern matching algorithm based on deterministic finite automata with faulty transition table

    Publication Year: 2010 , Page(s): 1 - 2
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (98 KB) |  | HTML iconHTML  

    Regular expression matching is the time-critical operation of many modern intrusion detection systems (IDS). This paper proposes pattern matching algorithm to match regular expression against multigigabit data stream. As usually used regular expressions are only subjectively tested and often generates many false positives/ negatives, proposed algorithm support the possibility to reduce memory requirements by introducing small amount of faults into the pattern matching. Algorithm is based on the perfect hashing and is suitable for hardware implementation. View full abstract»

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  • HELIOS: A High Energy-efficiency Locally-scheduled Input-queued Optical Switch

    Publication Year: 2010 , Page(s): 1 - 2
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (606 KB) |  | HTML iconHTML  

    Fast growing traffic for both the Internet and within data centers has lead to an increasing demand for high-speed switching systems. In this paper, we propose a fully distributed scheduling algorithm with an O(1) complexity, for a switch with an optical switching fabric. The inputs only use local queue information to make their scheduling decisions, and the switch consumes much less power than an electronic switch. Therefore, we call the switch HELIOS: High Energy-efficiency Locally-scheduled Input-queued Optical Switch. HELIOS can achieve 100% throughput for any admissible Bernoulli i.i.d traffic. To our knowledge, this is the first distributed scheduling algorithm to guarantee 100% throughput for an input-queued optical switch. View full abstract»

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  • A traffic-aware top-N firewall ruleset approximation algorithm

    Publication Year: 2010 , Page(s): 1 - 2
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (96 KB) |  | HTML iconHTML  

    Packet classification is widely used in various network security and operation applications. Two of the main challenges are the increasing number of classification rules, amount of traffic and network line speed. In this poster, we investigate an approximation algorithm for selecting the top-N most frequently matched subset of rules from the original ruleset. Through simulations, we show that our approaches the optimal while runs in seconds, allowing online adaptation to changing traffic patterns. View full abstract»

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  • Bit-shuffled trie: A new approach for IP address lookup

    Publication Year: 2010 , Page(s): 1 - 3
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (173 KB) |  | HTML iconHTML  

    IP address lookup is a fundamental operation in packet forwarding. Using multi-level index tables to find out the next-hop value is an attractive approach due to its simplicity. However, memory efficiency is relatively low because prefixes are sparsely distributed in the address space. In this poster, we shall outline a new approach to construct memory efficient index tables based on a technique called bit-shuffling. The proposed method is evaluated using a real-life IPv4 routing table with 321K prefixes. The lookup tables occupy 0.8MB memory. View full abstract»

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  • Efficient packet classification algorithm based on entropy

    Publication Year: 2010 , Page(s): 1 - 2
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (102 KB) |  | HTML iconHTML  

    This paper deals with packet classification in high-speed networks. It introduces a novel method for packet classification based on the amount of information stored in the ruleset. Basic principles of the algorithm based on the effort to reduce the amount of the necessary memory space and number of computational steps are presented together with analysis of the input rulesets. View full abstract»

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  • Fast regular expression matching in hardware using NFA-BDD combination

    Publication Year: 2010 , Page(s): 1 - 2
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (71 KB) |  | HTML iconHTML  

    The development of Network Intrusion Detection Systems (NIDS) is nowadays a powerful solution to defend against various network security threats. There has been a lot of research effort devoted to hardware-based NIDS, because of (1) the massive amount of computation performed by regular expression matching algorithms and (2) the gigabit per second performance requirement of modern NIDS. Hardware-based NIDS take advantage of parallelization inherent in FPGAs, ASICs or network processors to support very high network speeds, while software approaches fail to do so. View full abstract»

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  • Improving PC-based OpenFlow switching performance

    Publication Year: 2010 , Page(s): 1 - 2
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (323 KB) |  | HTML iconHTML  

    In this paper, we propose an architectural design to improve lookup performance of OpenFlow switching in Linux using a standard commodity network interface card based on the Intel 82599 Gigabit Ethernet controller. We describe our design and report our preliminary results that show packet switching throughput increasing up to 25 percent compared to the throughput of regular software-based OpenFlow switching. View full abstract»

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  • NFA split architecture for fast regular expression matching

    Publication Year: 2010 , Page(s): 1 - 2
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (84 KB) |  | HTML iconHTML  

    Many hardware architectures have been designed to accelerate regular expression matching in network security devices, but most of them can achieve high throughput only for strings or small sets of regular expressions. We propose new NFA Split architecture which reduces the amount of consumed FPGA resources in order to match larger set of regular expressions. New algorithm is introduced to find non-collision sets of states and determine part of nondeterministic automaton which can be mapped to the memory based architecture. For all analysed sets of regular expressions, the algorithm was able to find non-collision sets with 67.8 % of states in average and reduces the amount of consumed flip-flops to 37.6 % and look-up tables to 63.9 % in average. View full abstract»

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  • Software-based implementations of updateable data structures for high-speed URL matching

    Publication Year: 2010 , Page(s): 1 - 2
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (84 KB) |  | HTML iconHTML  

    URL matching is used in many network applications, including URL blacklisting, URL-based forwarding and URL shortening services. These applications need fast URL queries and updates, thus requiring an efficient updateable data structure. As the processing power of general-purpose multi-core processors increases, software-based approaches are better able to meet the speed requirements of URL matching. In this paper, we present our preliminary performance study of finite-automata- and hash-based URL matching implementations on commodity PCs. The impacts of the cache and memory allocation methods are discussed. View full abstract»

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  • Throughput of random arbitration for approximate matchings

    Publication Year: 2010 , Page(s): 1 - 2
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (182 KB) |  | HTML iconHTML  

    Exact matchings have been extensively studied in the past, but there is relatively little work about approximate matchings. We present a throughput analysis when random arbitration is used to obtain approximate matchings. We compute the throughput by the average available credits at outputs, which is obtained through a DTMC modeling. We also devise an iterative solving procedure for the DTMC of available output credits, based on the received grants at inputs. Both our analytical and simulation results show that applying random arbitration on the studied architecture containing a moderate buffer size (B > 8) yields almost hundred percent throughput. View full abstract»

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  • Efficient lookahead routing and header compression for multicasting in networks-on-chip

    Publication Year: 2010 , Page(s): 1 - 10
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1602 KB) |  | HTML iconHTML  

    As technology advanced, Chip Multi-processor (CMP) architectures have emerged as a viable solution for designing processors. Networks-on-Chip (NOCs) provide a scalable communication method for CMP architectures as the number of cores is increasing. Although there has been significant research on NOC designs for unicast traffic, the research on the multicast router design is still in infancy stage. Considering that one-to-many (multicast) and one-to-all (broadcast) traffic are more common in CMP applications, it is important to design a router providing efficient multicasting. In this paper, we propose an efficient lookahead routing with limited area overhead for a recently proposed multicast routing algorithm, Recursive Partitioning Multicast (RPM). Also, we present a novel compression scheme for a multicast packet header that becomes a big overhead in large networks. Comprehensive simulation results show that with our route computation logic design, providing lookahead routing in the multicast router only costs less than 20% area overhead and this percentage keeps decreasing with larger network sizes. Compared with the basic lookahead routing design, our design can save area by over 50%. With header compression and lookahead multicast routing, the network performance is improved by 22% in a (16 × 16) network on average. View full abstract»

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  • Energy-aware routing in hybrid optical network-on-chip for future Multi-Processor System-on-Chip

    Publication Year: 2010 , Page(s): 1 - 9
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (176 KB) |  | HTML iconHTML  

    With the development of Multi-Processor System-on-Chip (MP-SoC) in recent years, the intra-chip communication is becoming the bottleneck of the whole system. Current electronic network-on-chip (NoC) designs face serious challenges, such as bandwidth, latency and power consumption. Optical interconnection networks are a promising technology to overcome these problems. In this paper, we study the routing problem in optical NoCs with arbitrary network topologies. Traditionally, a minimum hop count routing policy is employed for electronic NoCs, as it minimizes both power consumption and latency. However, due to the special architecture of current optical NoC routers , such a minimum-hop path may not be energy-wise optimal. Using a detailed model of optical routers we reduce the energy-aware routing problem into a shortest-path problem, which can then be solved using one of the many well known techniques. By applying our approach to different popular topologies, we show that the energy consumed in data communication in an optical NoC can be significantly reduced. We also propose the use of optical burst switching (OBS) in optical NoCs to reduce control overhead, as well as an adaptive routing mechanism to reduce energy consumption without introducing extra latency. Our simulation results demonstrate the effectiveness of the proposed algorithms. View full abstract»

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