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Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd

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Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd

Date 3-8 Oct. 2010

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Title History

[Front cover]

[Front inside cover]

[Copyright notice]

General chair's welcome

History of the EOS/ESD symposium

Technical Program Committee 2010

Table of contents

A scalable Verilog-A modeling method for ESD protection devices

TCAD study of the impact of trigger element and topology on silicon controlled rectifier turn-on behavior

A novel physical model for the SCR ESD protection device

The relevance of long-duration TLP stress on system level ESD design

CDM simulation study of a system-in-package

Triggering of transient latch-up (TLU) by system level ESD

Measurement, simulation and reduction of EOS damage by electrical fast transients on AC power

SPICE simulation methodology for system level ESD design

TLP characterization for testing system level ESD performance

On-chip system level protection of FM antenna pin

An ESD design automation framework and tool flow for nano-scale CMOS technologies

Hierarchical verification of chip-level ESD design rules

An automated ESD verification tool for analog design

Predictive full circuit ESD simulation and analysis using extended ESD compact models: Methodology and tool implementation

Cross domain protection analysis and verification using whole chip ESD simulation

Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation

Impact of the power supply on the ESD system level robustness

Effects of TVS integration on system level ESD robustness

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