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2010 15th CSI International Symposium on Computer Architecture and Digital Systems

Date 23-24 Sept. 2010

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Displaying Results 1 - 25 of 62
  • [Title page]

    Publication Year: 2010, Page(s): I
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  • [Blank page]

    Publication Year: 2010, Page(s): IV
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  • Table of contents

    Publication Year: 2010, Page(s):V - VII
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  • [Blank page]

    Publication Year: 2010, Page(s): VIII
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  • Message from the chairs

    Publication Year: 2010, Page(s): IX
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  • Organizing Committee

    Publication Year: 2010, Page(s): X
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  • Program Committee

    Publication Year: 2010, Page(s): XI
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  • [Blank page]

    Publication Year: 2010, Page(s): XII
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  • Sustainable digital infrastructure

    Publication Year: 2010, Page(s): XIII
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    Summary form only given. Modern society is built upon information and communications technologies that have permeated all aspects of our lives. Industries including e-commerce, healthcare, media, and finance are all dependent on network access to data and media services for their daily operations. Taken together, the hardware, software, and organizations that work together to provide network acces... View full abstract»

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  • [Blank page]

    Publication Year: 2010, Page(s): XIV
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  • Designing many-core platforms for silicon-efficient embedded multimedia computing

    Publication Year: 2010, Page(s): XV
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (38 KB) | HTML iconHTML

    Summary form only given. Programmability is a key requirement for fast time-to-market and agile adaptation to rapidly evolving multimedia standards and customer expectations. Unfortunately, programmable architectures come with order-of-magnitude computational density and energy efficiency gaps with respect to custom-fit hardware. Is there a way to escape the flexibility vs. efficiency dualism? Is ... View full abstract»

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  • [Blank page]

    Publication Year: 2010, Page(s): XVI
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  • Towards energy-scalable data centers

    Publication Year: 2010, Page(s): XVII
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (38 KB)

    Summary form only given. Technology forecasts indicate that device scaling will continue well into the next decade. Unfortunately, it is becoming extremely difficult to harness this increase in the number of transistors into performance due to a number of technological, circuit, architectural, methodological and programming challenges. In this talk, I will argue that the key emerging showstopper i... View full abstract»

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  • [Blank page]

    Publication Year: 2010, Page(s): XVIII
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  • Session 1: Arithmetic

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

    Publication Year: 2010, Page(s): 2
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  • Posibits, negabits, and their mixed use in efficient realization of arithmetic algorithms

    Publication Year: 2010, Page(s):3 - 9
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (341 KB) | HTML iconHTML

    Positively weighted and negatively weighted bits (posibits, negabits) have been used in the interpretation of 2's-complement, negative-radix, and binary signed-digit number representation schemes as a way of facilitating the development of efficient arithmetic algorithms for various application domains. In this paper, we show that a more general view of posibits and negabits, along with their mixe... View full abstract»

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  • [Blank page]

    Publication Year: 2010, Page(s): 10
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  • Optimization and evaluation of the reconfigurable Grid Alu Processor

    Publication Year: 2010, Page(s):11 - 18
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB) | HTML iconHTML

    Currently few architectural approaches propose new paths to raise the performance of conventional sequential instruction streams in the time of the billions transistor era. Many application programs could profit from processors that are able to speed up the execution of sequential applications beyond the performance of current superscalar processors. The Grid Alu Processor (GAP) is a runtime recon... View full abstract»

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  • M-ary parallel modular exponentiation: Software vs. hardware

    Publication Year: 2010, Page(s):19 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB) | HTML iconHTML

    Most of cryptographic systems are based on modular exponentiation. It is performed using successive modular multiplications. One way of improving the throughput of a cryptographic system implementation is reducing the number of the required modular multiplications. Existing methods attempt to reduce this number by partitioning the exponent in constant or variable size windows. In this paper, in th... View full abstract»

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  • Session 2: SoCs and NoCs

    Publication Year: 2010, Page(s): 25
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  • [Blank page]

    Publication Year: 2010, Page(s): 26
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  • Variation-aware task scheduling and power mode selection for MPSoC power optimization

    Publication Year: 2010, Page(s):27 - 33
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2120 KB) | HTML iconHTML

    Increasing delay and power variation has become a major challenge to designing high performance Multiprocessor System-On-Chips (MPSoC) in deep sub-micron technologies. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable. In this paper, we propose a static variation-aware task scheduling and power mode selection algo... View full abstract»

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  • [Blank page]

    Publication Year: 2010, Page(s): 34
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  • Pipeline-based interlayer bus structure for 3D networks-on-chip

    Publication Year: 2010, Page(s):35 - 41
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (622 KB) | HTML iconHTML

    The structure of direct vertical interconnections, called Through Silicon Vias (TSVs), is an important issue in the realm of 3D ICs. The bus-based and network-based structures are the two dominant architectures for implementing TSVs as interlayer connection in 3D ICs. Both implementations have some disadvantages. The former suffers from poor scalability and deteriorates the performance at high inj... View full abstract»

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