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System on Chip (SoC), 2010 International Symposium on

Date 29-30 Sept. 2010

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  • [Front and back cover]

    Publication Year: 2010, Page(s):c1 - c4
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  • [Title page]

    Publication Year: 2010, Page(s): 1
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  • [Copyright notice]

    Publication Year: 2010, Page(s): 1
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  • [Advertisement]

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • Foreword

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

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  • Organizing Committee

    Publication Year: 2010, Page(s): 1
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  • External reviewers

    Publication Year: 2010, Page(s): 1
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  • Accepted papers by country

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • Plenary presentations

    Publication Year: 2010, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (25 KB)

    Provides an abstract for each of the plenary presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • Table of contents

    Publication Year: 2010, Page(s): 1
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  • Table of contents

    Publication Year: 2010, Page(s): 1
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  • Table of contents

    Publication Year: 2010, Page(s): 1
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  • Table of contents

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

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  • Author index

    Publication Year: 2010, Page(s): 1
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  • Author index

    Publication Year: 2010, Page(s): 1
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  • Author index

    Publication Year: 2010, Page(s): 1
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  • Author index

    Publication Year: 2010, Page(s): 1
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  • Optimized communication architecture of MPSoCs with a hardware scheduler: A system view

    Publication Year: 2010, Page(s):163 - 168
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (282 KB) | HTML iconHTML

    With increasing complexity of MPSoCs, efficient runtime management of system resources becomes of vital importance for improving the system performance and energy efficiency. OSIP-an operating system application-specific instruction-set processor - provides a promising solution to this. It delivers high computational performance to deal with dynamic task scheduling and mapping, while still being p... View full abstract»

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  • Skip-links: A dynamically reconfiguring topology for energy-efficient NoCs

    Publication Year: 2010, Page(s):49 - 54
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (166 KB) | HTML iconHTML

    We introduce the Skip-link architecture that dynamically reconfigures Network-on-Chip (NoC) topologies, in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating op... View full abstract»

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  • Implementation and benchmarking of FFT algorithms on multicore platforms

    Publication Year: 2010, Page(s):59 - 62
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (68 KB) | HTML iconHTML

    This paper analyzes the performance of the execution of a few commonly used versions of the Fast Fourier Transform (FFT) algorithm. We started from the C implementation of programs implementing the aforementioned FFT algorithms, then profiled their execution on a series of multicore platforms, both embedded and not. The aim of this work is multiple: in the first place we tried to find out how well... View full abstract»

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