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Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in

Date 22-24 Sept. 2010

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Displaying Results 1 - 25 of 107
  • [Front cover]

    Publication Year: 2010 , Page(s): c1
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  • [Front matter]

    Publication Year: 2010 , Page(s): i - xiv
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  • Technical program

    Publication Year: 2010 , Page(s): 1 - 22
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  • Author index

    Publication Year: 2010 , Page(s): 1 - 23
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  • An improved neutral-point-potential balance control strategy for three-level PWM rectifier

    Publication Year: 2010 , Page(s): 1 - 4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (114 KB) |  | HTML iconHTML  

    Neutral point potential balance control is very important to three-level neutral-point-clamped (NPC) rectifiers. In this paper, the balance control strategy is studied with three-level space vector pulse width modulation (SVPWM) algorithm based on reference voltage decomposition. An improved neutral-point potential balance control strategy based on balance factor is proposed and the principle is analyzed. Simulation and experimental results verify the validity of the control strategy. View full abstract»

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  • FPGA based embedded implement of space vector pulse width modulation

    Publication Year: 2010 , Page(s): 5 - 8
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    This paper introduces the working principle of space vector pulse width modulation (SVPWM), and presents a new circuit realization of SVPWM generator based on FPGA-embedded technique. MicroBlaze is a 32-bit high-performance processor embedding in the FPGA chip, and the left logical units can be used to design IP cores that needed, thus software and hardware can be combined to realize this SVPWM control system. The proposed SVPWM control scheme can be realized using a single FPGA chip. This scheme contains the advantages of SVPWM generator and FPGA-embedded technique, thus being important for high performance control system, and a new way for the design of high-performance motion control systems is provided. View full abstract»

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  • Design and implementation of a novel programmable power monitor chip

    Publication Year: 2010 , Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (286 KB) |  | HTML iconHTML  

    This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5 v to 5.0 v with 0.1 v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation is based on 2M1P 0.5 μm mixed signal process, the die area is 0.24mm2, and the quiescent current is only 3 uA. View full abstract»

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  • Design of wireless power supply microsystem for capsule endoscope

    Publication Year: 2010 , Page(s): 13 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (237 KB) |  | HTML iconHTML  

    A novel wireless powering solution for active capsule endoscope has been presented in this paper. The self-resonant coil inside the human body is used to receive energy, and the energy is rectified and regulated to generate a stable voltage for charging a button battery, which provides stable power for controlling and driving the system by the low dropout (LDO) regulator fixed in the capsule endoscope. The charging microsystem is designed using a 0.18 μm CMOS high voltage process. Simulation results indicate that the rectifier conversion efficiency of voltage and power is about 82.14% and 83.50%, respectively. The regulator and LDO provide relatively constant output voltage in spite of the variations of input voltage and loading current. The design of power management integrated circuits meets the requirement for controlling the charging-recharging of the battery and providing stable voltage for the control and drive system of the capsule endoscope. View full abstract»

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  • A high quality CMOS power regulator for a wireless endoscope

    Publication Year: 2010 , Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (133 KB) |  | HTML iconHTML  

    In this paper, we present the design of a low-power, high-power supply rejection ratio (PSRR) power regulator used in telemetry-powered bioimplantable microsystems in a 0.35μm standard CMOS process. The power regulator is comprised of a CMOS full-wave bridge rectifier, a wide-range and high PSRR voltage reference and a low drop out series voltage regulator. Simulation results show the proposed circuit provides 3V regulated DC output, exhibits load regulation factor of as low as 1% when delivering up to 30mA load current, and demonstrates line regulation factor of as low as 0.01%/V over 4.8V input amplitude variation. View full abstract»

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  • Switching activity estimation of CIC filter integrators

    Publication Year: 2010 , Page(s): 21 - 24
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (114 KB) |  | HTML iconHTML  

    In this work, a method for estimation of the switching activity in integrators is presented. To achieve low power, it is always necessary to develop accurate and efficient methods to estimate the switching activity. The switching activities are then used to estimate the power consumption. In our work, the switching activity is first estimated for the general purpose integrators and then it is extended for the estimation of switching activity in cascaded integrators in CIC filters. View full abstract»

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  • Design and implementation of an optimized FIR filter for IF GPS signal simulator

    Publication Year: 2010 , Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (139 KB) |  | HTML iconHTML  

    This paper presents the design and implementation of a forty-order FIR filter for IF GPS signal simulator with three algorithms: multiply and accumulate (MAC), add-and-shift scheme with CSD encoding (CSD), new common sub-expression elimination (CSE). Each scheme is analyzed in detail including design and optimization process to find the best one with the least hardware resource and power consumption. The FIR filter is coded in Verilog HDL, and then implemented using Xilinx Virtex5 FPGA and Design Compiler based on SMIC 0.18 um technology. FPGA implementation result shows that CSE consumes the least total occupied slice, with 63% and 20% reduction compared with MAC and CSD. The implementation of CSE in ASIC also proves 66% and 13% reduction in total chip area, as well as 36% and 6% dynamic power reduction compared with MAC and CSD respectively. View full abstract»

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  • Design of dual-supply dual-ground voltages domino circuits

    Publication Year: 2010 , Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB) |  | HTML iconHTML  

    A low power dual-supply dual-ground voltages domino circuit is presented in this paper. The domino circuit employs a high ground voltage and the shared-well technique to improve the dual-supply voltage technology and further reduce the power consumption and optimize the layout area. Based on Chartered 0.35 um 2P4M CMOS technology, simulation results shows that dual-supply dual-ground voltages domino circuits save power up to 25% as compared to conventional domino circuits under the similar speed. View full abstract»

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  • An energy recovery D flip-flop for low power semi-custom ASIC design

    Publication Year: 2010 , Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (363 KB) |  | HTML iconHTML  

    A sense amplifier D flip-flop with reset function using energy recovery technique, SAERDR (Sense Amplifier Energy Recovery D Flip-flop with Reset Function), is presented. The proposed flip-flop operates with a single phase sinusoidal clock to recover the energy of the clock pin. Simulation results show that the power consumption of clock pin is saving 72% on average as compared to the same implementation using the square-wave clocking scheme for clock frequencies ranging from 10MHz to 60MHz. We also propose a methodology to design a semi-custom energy recovery ASIC using SAERDR. In the SMIC 0.13μm CMOS process, a numerical controlled oscillator using our methodology is implemented. Test results show the total power saving is up to 34.9% as compared to the implementation using the conventional D flip-flops MSD (Master Salve D Flip-flop) at 60MHz. View full abstract»

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  • Implementation of telephone remote control system based on FPGA

    Publication Year: 2010 , Page(s): 37 - 40
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (539 KB) |  | HTML iconHTML  

    This paper presents an intelligent control system with the ability of remote control based on a public telephone communication network. The remote operation with user authority by transmitting password and operation code through telephone network is realized by using a FPGA controller. The main function circuits of the designed system include ring detector, DTMF decoder, pick-phone circuit, audio prompt, and the FPGA controller. The system has highly configurable, stable and reliable feature. View full abstract»

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  • Swarm Intelligence based circuit partitioning

    Publication Year: 2010 , Page(s): 41 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (71 KB) |  | HTML iconHTML  

    This paper presents a swarm Intelligence based circuit partitioning technique using particle swarm optimization method. The circuit is divided into partitions and number of interconnections between them is minimized. The proposed method gives excellent results in solving the stochastic problem of circuit partitioning. View full abstract»

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  • A loop-centric profiling method for embedded applications

    Publication Year: 2010 , Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (91 KB) |  | HTML iconHTML  

    Embedded applications usually impose tight constraints upon their code efficiency, which entail elaborate code optimization on the hotspot of the programs. In order to identify the hotspot, we propose an effective and easy-use loop-centric profiling method in this paper. In our proposed method, a code isolation step is first applied on the original code, which extracts all the candidate loops at source level and keeps the original semantic unchanged. Then we can use an off-the-shelf profiling tool to identify our interested loops in the program on a given platform. Our method is retargetable as long as the profiler for the target platform is available. In our experiments, we tested our method using the MPEG-2 decoder application on ARM platform, and we can see that the results provide helpful information for further optimization on the application code. View full abstract»

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  • An efficient VLSI circuit extraction algorithm for transistor-level to gate-level abstraction

    Publication Year: 2010 , Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (119 KB) |  | HTML iconHTML  

    This paper proposes an efficient VLSI extraction algorithm to extract a transistor level netlist to a gate level netlist for functional verification and diagnosis. Compared with other reported circuit extraction algorithm, our proposed technique does not require a cell library and is able to generate Boolean equations without the prior knowledge of transistor type or drain/source orientation of the transistors in the netlist. The proposed algorithm firstly transforms the netlist into a matrix. Secondly, the output nodes of different gates are detected using a pre-sorting comparison algorithm. Then, respective pull-up networks (PUNs) and pull-down networks (PDNs) are identified by a depth-first search algorithm. Finally, the function of the PUN/PDN is verified and stored in terms of Boolean equations. The results on 10 standard cells and 6 testing circuits show that the algorithm performs a near-linear time operation. For a 30-transistor standard cell (XOR4), the time required to complete the extraction is 35.4ms, and for a 3639-transistor combinational circuit, the time required to complete the extraction is around 114.4sec. Compared with the reported technique, our proposed algorithm has an average of 8.4% reduction in CPU time. View full abstract»

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  • Design of PIONEER: A case study using NoGap

    Publication Year: 2010 , Page(s): 53 - 56
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (147 KB) |  | HTML iconHTML  

    Application Specific Instruction-set Processors (ASIPs) are needed to handle the future demand of flexible yet high performance computation in mobile devices. The flexibility of ASIPs makes them preferable over fixed function Application Specific Integrated Circuits (ASICs). Also, a well designed ASIP, has a power consumption comparable to ASICs. However the cost associated with ASlP design is a limiting factor for a more wide spread adoption. A number of different tools have been proposed, promising to ease this design process. However all of the current state of the art tools limits the designer due to a template based design process. We have therefore proposed the Novel Genrator of Accelerators And Processors (NoGap). NoGap is a design automation tool for ASIP design that puts very few limits on the designer, yet it supports a designer by automating much of the tedious and error prone tasks associated with ASIP design. This paper presents a case study, where we have used NoGap to design a Reduced Instruction Set Computing (RISC) processor, with DSP extensions, which we named PIONEER. The NoGap generated System Verilog code was synthesized using both an FPGA and ASIC flow. With no FPGA specific optimizations, PIONEER meet timing closure at 203 MHz in a Virtex-4 LX80 speed grade 12. PIONEER was successfully tested in an FPGA by running some typical Digital Signal Processor (DSP) application such as Finite Impulse Response (FIR) filters, and a Discrete Cosine Transform (DCT). area and power consumption of the ASIC design was 24815 μm2 and 1.607 mW (estimated) respectively. Time closure where met at 300 MHz. Examining the critical paths we could conclude that hardware synthesized by NoGap was not a limiting factor. View full abstract»

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  • Cycle accurate simulator generator for NoGap

    Publication Year: 2010 , Page(s): 57 - 60
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    Application Specific Instruction-set Processors (ASIPs) are needed to handle the future demand of flexible yet high performance computation in mobile devices. However designing an ASIP is complicated by the fact that not only the processor but, also tools such as assemblers, simulators, and compilers have to be designed. Novel Generator of Accelerators And Processors (NoGap), is a design automation tool for ASIP design that imposes very few limitations on the designer. Yet NoGap supports the designer by automating much of the tedious and error prone tasks associated with ASIP design. This paper will present the techniques used to generate a stand alone software simulator for a processor designed with NoGap. The focus will be on the core algorithms used. Two main problems had to be solved, simulation of a data path graph and simulation of leaf functional units. The concept of sequentialization is introduced and the algorithms used to perform both the leaf unit sequentialization and data path sequentialization is presented. A key component of the sequentialization process is the Micro Architecture Generation Essentials (Mage) dependency graph. The mage dependency graph and the algorithm used for its generation are also presented in this paper. A NoGap simulator was generated for a simple processor and the results were verified. View full abstract»

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  • Performance modeling of high speed VLSI interconnects

    Publication Year: 2010 , Page(s): 61 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (315 KB) |  | HTML iconHTML  

    This paper presents a model order reduction technique based on balancing-free square root (BSR) method for high speed coupled integrated circuit interconnects. The salient features of this technique are the less CPU time resulting from the passivity of the reduced transfer function, and the availability of provable weighted error bounds for the reduced-order system. This paper also shows that the balancing-free square root method produces reduced systems that accurately follow the time- and frequency-domain responses of the original system. All the experiments have been carried out using Cadence Design Simulator which indicate that the proposed BSR achieves more accuracy with less CPU time than the other model order reduction techniques existing in literature. View full abstract»

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  • A novel design of dual ladder resistor D/A converter

    Publication Year: 2010 , Page(s): 65 - 68
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB) |  | HTML iconHTML  

    This paper presents a novel dual ladder resistor D/A converter architecture. A 10 bits D/A converter is implemented which is based on this architecture. The present architecture provides a novel decoding scheme for dual ladder resistor D/A converter that reduces the size of the decoding logic, reduces the number of switches in coarse resistor stage and fine resistor stage. Experience of the 10 bits D/A converter design was shared. The design achieves INL and DNL of +0.3/-0.4LSB, +0.5/-0.4 LSB. This 10 bits D/A converter was used in reference voltage source chip which was taped out by Chartered 0.35μm CMOS 2P4M Mixed-mode process. View full abstract»

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  • Cascade 2–2 sigma-delta modulators for wideband high-resolution applications

    Publication Year: 2010 , Page(s): 69 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (197 KB) |  | HTML iconHTML  

    In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been proposed in this paper. First, a MASH 2-2 with feed-forward topology in both stages has been explained to obtain low-distortion property and remove subtraction Second, a flexible SMASH 2-2 has been proposed to choose appropriate coefficients for different requirements. Third, a SMASH 2-2 with feed-forward quantization noise self-coupled structure has been displayed to cancel quantization error of the preceding stage totally. Detailed simulation results and comparisons demonstrate the performance of these topologies. View full abstract»

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  • A 1-V 42.6-μW 1.5-bit continuous-time Delta-Sigma modulator for audio applications

    Publication Year: 2010 , Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB) |  | HTML iconHTML  

    A fourth-order continuous-time (CT) Delta-Sigma modulator with 1.5-bit quantizer is presented in this paper. This design is targeted for audio applications that demand high resolution, low supply voltage, and low power consumption. The input-feedforward topology, with optimized coefficients, is utilized to reduce internal signal swings as well as the power consumption. A 1.5-bit quantizer with simple dynamic element matching (DEM) is used to improve resolution and stability. A novel feedforward and summation structure is applied in the 1.5-bit modulator to reduce the power consumption and the chip area, and to simplify the circuit. The modulator, designed in a 0.13-μm CMOS technology, achieves 100.5-dB peak SQNR (Signal-to-Quantization Noise Ratio), and 97.5-dB peak SQNDR (Signal-to-Quantization Noise-and-Distortion Ratio) over a 20-kHz signal bandwidth with a 2.56-MHz clock. The power consumption of the modulator is 42.6 μW under a 1-V supply, and the chip core area is 0.13 mm2. View full abstract»

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  • Adaptive calibration of gain and offset errors for time-interleaved ADCs

    Publication Year: 2010 , Page(s): 77 - 80
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (135 KB) |  | HTML iconHTML  

    Time-interleaved (TI) Analog-to-Digital Converters (ADC) are efficient for high-speed data acquisition. However, mismatches among different channels in a TIADC system due to manufacturing process variations cause distortion in the sampled signal and degrade the SNR and SFDR significantly. The offset and gain mismatches are the two important error sources for the TIADC system. In this paper, a methodology based on Least Mean Square (LMS) adaptive algorithm is proposed for simultaneous compensation of the gain and offset mismatches. The proposed method is also adaptive to the slow changes of the mismatches caused by temperature variation and aging effect. Numerical simulations are conducted to validate the adaptive algorithm. View full abstract»

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  • Towards realizing variable resolution analog to digital converters

    Publication Year: 2010 , Page(s): 81 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB) |  | HTML iconHTML  

    In this paper, the idea of variable resolution ADCs is proposed and implemented for all types of ADC architectures. A novel peak-detector circuit is employed to achieve variable resolution as well as to switch the unused sections of the ADCs to standby mode. Linear reduction in resolution leads to exponential reduction in power. The ADCs are capable of operating at 4-12 bit precision at a supply voltage of 2.5V. The sampling frequency ranges from 1.8MSPS to 1.2 GSPS that depends on ADC topologies. Variable-resolution flash, semi - flash, pipelined and SAR ADCs operating at a maximum resolution of 8-bit, 12-bit, 12bit, 10-bit respectively have been designed and verified for post layout simulations in standard 65nm CMOS technology. View full abstract»

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