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Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)

5-5 June 1998

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  • Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)

    Publication Year: 1998
    Request permission for commercial reuse | PDF file iconPDF (1789 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1998, Page(s):225 - 226
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    Freely Available from IEEE
  • Implementation of an RTLS blind equalization algorithm on DSP

    Publication Year: 1998, Page(s):150 - 155
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    Blind equalization has been a very active area of research during the last years. Research is mostly focused on performance without too much attention on the complexity of the presented techniques. However, the high complexity of these blind algorithms coupled with the high data rates of mobile telecommunications may hamper a practical implementation. Recently we presented a recursive total least ... View full abstract»

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  • Testing prototypes validity to enhance code reuse

    Publication Year: 1998, Page(s):6 - 12
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    The complexity of distributed systems is a problem when designers want to evaluate their safety and liveness. Often, they are built by integration of existing components with newly developed ones. Actually it is valuable to handle the integration of external pieces of software in the specification and testing activities. However it is difficult to validate them formally unless doing reverse-engine... View full abstract»

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  • Behavioral emulation of synthesized RT-level descriptions using VLIW architectures

    Publication Year: 1998, Page(s):70 - 75
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    Describes techniques that allow VLIW architectures to be used for the behavioral emulation of RT-level descriptions. The starting point of the techniques is a behavioral description at the algorithmic level, e.g. VHDL. This description is transformed into RT-level descriptions of the datapath and controller. The controller is given as a finite state machine. We show how to map these descriptions o... View full abstract»

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  • Rapid design of discrete orthonormal wavelet transforms

    Publication Year: 1998, Page(s):142 - 147
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    A methodology which allows a non specialist to rapidly design silicon wavelet transform cores has been developed. This methodology is based on a generic architecture utilising time interleaved coefficients for the wavelet transform filters. The architecture is scaleable and it has been parameterised in terms of wavelet family, wavelet type, data word length and coefficient word length. The control... View full abstract»

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  • Using CDIF for concept-oriented rapid prototyping of electronic systems

    Publication Year: 1998, Page(s):182 - 187
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    An open environment for heterogeneous system design is presented supporting all design phases. Our approach separates front end tools with structural and behavioral modeling from back end tools for analysis, simulation and emulation. This separation is realized with the emerging CASE data interchange format CDIF. Though CDIF is intended as an interchange format for the interchange of modeling data... View full abstract»

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  • Rapid prototyping of embedded hardware/software systems

    Publication Year: 1998, Page(s):2 - 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (16 KB)

    Prototyping of embedded hardware/software systems is increasingly important because the difference in the product relies mainly on the variations of software and system features. Nonfunctional and software requirements must be explored together with the user. It is important to integrate the user into the specification process because more and more customers expect solutions and services tailored ... View full abstract»

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  • OMI-compliant model for virtual emulation

    Publication Year: 1998, Page(s):64 - 69
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    In this paper, the virtual emulation problem is addressed. We give sufficient conditions for a digital system to be emulable. Moreover, we present sufficient conditions under which system emulation can degenerate from an event-driven to a faster cycle-based simulation. The OMI (Open Model Interface), an emerging standard modeling interface for digital systems, has been considered to develop an emu... View full abstract»

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  • FLYSIG: dataflow oriented delay-insensitive processor for rapid prototyping of signal processing

    Publication Year: 1998, Page(s):136 - 141
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    As the one-chip integration of HW modules designed by different companies becomes more and more popular, reliability of a HW design and evaluation of the timing behavior during the prototype stage are absolutely necessary. One way to guarantee reliability is the use of robust design styles, e.g., delay insensitivity. For early timing evaluation, two aspects must be considered: a) the timing needs ... View full abstract»

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  • Code generation of data dominated DSP applications for FPGA targets

    Publication Year: 1998, Page(s):162 - 167
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    The VHDL code generator of the GRAPE rapid prototyping and design environment has been extended to support a much wider range of data dominated applications. We describe the approach taken to implement CSDF applications on FPGAs, including the automatic code generation for task communication and scheduling on FPGAs alone or in conjunction with DSP processors. The implementation choices are discuss... View full abstract»

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  • A prototyping system for high performance communication systems

    Publication Year: 1998, Page(s):84 - 88
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB)

    Presents a prototyping platform for high-performance communication systems together with a design methodology. Based on a formal design entry and nonfunctional design goals such as execution time and overall system cost, a software/hardware partitioning is generated and its performance is estimated with formal models. Valid partitionings are then implemented on a prototyping platform which is base... View full abstract»

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  • Towards a rapid prototyping by linking design, implementation and debugging in real-time parallel systems

    Publication Year: 1998, Page(s):194 - 199
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB)

    Due to the culture of sequential programming, the lack of tools and the inherent difficulties of parallel programming, most programmers find it hard to design and evaluate real time parallel programs. As a result, a major problem found in the development of real time parallel systems is the difficulty to produce rapid prototypes of the application and frequently the development of these types of s... View full abstract»

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  • Virtual prototyping of a digital neural current controller

    Publication Year: 1998, Page(s):176 - 181
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (72 KB)

    The paper describes a significant case study of virtual prototyping in modern digital electronics. It outlines the design process of a neural predictive current controller for VSI-PWM inverters. MATLAB simulations of power system behaviour were initially performed to check the viability of the principles underlying the operation of the new controller. The controller was designed and tested using V... View full abstract»

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  • The Plastic Cell Architecture for dynamic reconfigurable computing

    Publication Year: 1998, Page(s):39 - 44
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB)

    The authors explain the dynamic manipulation of the object as an essential function which a general purpose computer should have. Introducing this property, they propose a general purpose reconfigurable computer architecture to obtain both performance of the wired logic and generality of the program logic. Since the proposing reconfigurable logic device is a mesh structure of the cell of high plas... View full abstract»

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  • APICES-rapid application development with graph pattern

    Publication Year: 1998, Page(s):25 - 30
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    The author present the novel software design environment APICES. It is specifically tailored to support rapid application development based on network like data structures which are typical for CAD tools, system level design tools or DSP applications. APICES is based on graph patterns. These graph patterns offer high-level functionality for beyond manipulation of simple graphs consisting of nodes ... View full abstract»

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  • Emulating large designs on small reconfigurable hardware

    Publication Year: 1998, Page(s):58 - 63
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    FPGA based hardware emulation is becoming very popular for checking the functional correctness of designs prior to fabrication. A design is partitioned and mapped on a programmable hardware system that consists of several FPGAs. Typically, as the design size increases, the utilization of FPGA devices tends to fall rapidly. This demands large amounts of hardware resources for emulating large design... View full abstract»

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  • RIFLE-62: a flexible environment for prototyping dynamically reconfigurable systems

    Publication Year: 1998, Page(s):130 - 135
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    The paper presents RIFLE-62-a new FPGA based prototyping environment optimised for rapid prototyping of applications exploiting dynamically reconfigurable logic (DRL). RIFLE-62 has a highly flexible architecture based around the Xilinx XC6200 family of dynamically reconfigurable FPGAs. The RIFLE-62 experimental board further provides two additional FPGAs (XC4013E and XC3100A), large static and dyn... View full abstract»

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  • Performance evaluation tool for rapid prototyping of hardware-software codesigns

    Publication Year: 1998, Page(s):218 - 224
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    Performance evaluation is essential for tradeoff analysis during rapid prototyping. Existing performance evaluation strategies based on co-simulation and static analysis are either too slow or error prone. We therefore present an intermediate approach based on profiling and scheduling for rapid prototyping of hardware-software codesigns. Our performance evaluation tool obtains representative task ... View full abstract»

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  • Rapid prototyping technology accelerates software development for complex network systems

    Publication Year: 1998, Page(s):113 - 115
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    In two projects involving highly complex networking systems, our group at Cisco used Aptix Corporation's rapid-prototyping technology for verification and software co-development. In the first project, the verification cost and time were cut nearly in half. In the second project, diagnostic code and part of the final driver software were ready before the actual system hardware was available. The s... View full abstract»

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  • A technique for combined virtual prototyping and hardware design

    Publication Year: 1998, Page(s):156 - 161
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    A technique to include virtual prototyping in the design cycle of complex digital modem ASICs is presented. It is innovating by using the same behavioral description for both the prototype as well as the final circuit implementation. Relating to verification of the design, this is a crucial benefit. The article discusses the prototyping mechanism by using the design of an upstream cable modem ASIC... View full abstract»

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  • Real time prototyping method and a case study

    Publication Year: 1998, Page(s):13 - 18
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    The paper presents a strategy for high-speed prototyping on FPGAs. The traditional “glue” synthesis strategy may not be sufficient for obtaining FPGA prototypes working at real speed. A key possibility to accelerate the performance of FPGA designs is the utilisation of the architectural features of modern FPGAs. To do this, no “push-button” solutions exists. The way to do t... View full abstract»

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  • An extensible, low cost rapid prototyping environment based on a reconfigurable set of FPGAs

    Publication Year: 1998, Page(s):78 - 83
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    Presents the architecture of a system for the rapid prototyping of digital circuits that is based an the Altera FLEX8000 reconfigurable set of FPGAs. The interconnection architecture of the system consists of both fixed lines between adjacent FPGAs and shared lines that are capable of interconnecting more than two devices. The reconfigurable set of devices is placed on a 2D grid. The external inte... View full abstract»

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  • A library of memory controllers for an image processing prototyping system

    Publication Year: 1998, Page(s):188 - 193
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    Memory organization has proven to be a key point when implementing image processing (IP) algorithms due to the changes in data formats along the process. The latency produced by memory access is in most cases responsible for the failure in achieving the temporal requirements of real time processing. We review the different memory organizations in real word real time image processing systems, and i... View full abstract»

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  • The video and image processing emulation system VIPES

    Publication Year: 1998, Page(s):170 - 175
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    We present a real time emulation system for complete video processing schemes. Our emulation system is based on a commercial FPGA emulator and related software. To meet real time constraints, we have extended this emulation environment by dedicated video interfaces, efficient flexible FPGA macros, and a modified design flow. The feasibility of this methodology is shown for a two dimensional discre... View full abstract»

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