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2010 IEEE Computer Society Annual Symposium on VLSI

5-7 July 2010

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Displaying Results 1 - 25 of 119
  • [Front cover]

    Publication Year: 2010, Page(s): C1
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  • [Title page i]

    Publication Year: 2010, Page(s): i
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  • [Title page iii]

    Publication Year: 2010, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2010, Page(s): iv
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  • Table of contents

    Publication Year: 2010, Page(s):v - xiii
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  • Message from General Chairs

    Publication Year: 2010, Page(s): xiv
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  • Organizing Committee

    Publication Year: 2010, Page(s):xv - xvi
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  • Program Committee

    Publication Year: 2010, Page(s):xvii - xviii
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  • European ICT Research: 2011-2012 Outlook for Components and Systems

    Publication Year: 2010, Page(s):1 - 2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (157 KB) | HTML iconHTML

    In 2011-2012, the European ICT research priorities are focused on a set of Challenges with mid-to-long term goals that require trans-national collaboration. Each Challenge is addressed through a limited set of objectives that form the basis for Calls for Proposals and lead to EU-funded research projects. One of the Challenges addresses "Alternative Paths to Components and Systems", it covers nanoe... View full abstract»

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  • Digital Microfluidic Biochips: A Vision for Functional Diversity and More Than Moore

    Publication Year: 2010, Page(s):3 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (183 KB) | HTML iconHTML

    Microfluidics-based biochips are revolutionizing high-throughput sequencing, parallel immunoassays, clinical diagnostics, and drug discovery. These devices enable the precise control of nanoliter volumes of biochemical samples and reagents. Compared to conventional laboratory procedures, which are cumbersome and expensive, miniaturized biochips offer the advantages of higher sensitivity, lower cos... View full abstract»

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  • Small Worlds: The Dynamics of NoCs in Tomorrow SoC Architecture

    Publication Year: 2010, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (122 KB) | HTML iconHTML

    Consumer electronics (CEs) is mainly characterized by its heterogeneity in products and markets. Moreover, large companies like Google, YouTube, Myspace, are revolutionizing the way to provide information contents. Today, several new CE devices have been introduced in the marketplace for receiving, visualizing, communicating, creating, and sending information. This changing implies that end-users ... View full abstract»

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  • Reconfigurable Architectures for Bioinformatics Applications

    Publication Year: 2010, Page(s):6 - 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB) | HTML iconHTML

    Reconfigurable technology offers great advantages in bioinformatics applications vs. general-purpose computing. The presentation outlined in this paper looks into the attributes of several bioinformatics algorithms which make them suitable for reconfigurable computing, the resulting architectures, and their performance tradeoffs vs. general-purpose computers, graphics processor units (GPU) and VLS... View full abstract»

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  • Challenges and Perspectives of Computer Architecture at the Nano Scale

    Publication Year: 2010, Page(s):8 - 10
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (202 KB) | HTML iconHTML

    Advances in nanotechnology and the research of new materials has led to the elaboration of nano-components with novel properties and functions. Exploring how those novel components could be used to devise future computer architectures, complementing rather than supplementing CMOS technology, is a new research subject known as Nanocomputing. In this talk we will present the major challenges of such... View full abstract»

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  • SUT-RNS Forward and Reverse Converters

    Publication Year: 2010, Page(s):11 - 16
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (389 KB) | HTML iconHTML

    Stored Unibit Transfer (SUT) has been recently proposed as a redundant high-radix encoding for the channels of a Residue Number System (RNS) that can improve the efficiency of conventional redundant RNS. In this paper we propose modulo 2n±1 forward and reverse converters for the SUT-RNS encoding. The proposed converters are based on parallel-prefix binary or modulo adders and are... View full abstract»

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  • Clock Tree Synthesis with XOR Gates for Polarity Assignment

    Publication Year: 2010, Page(s):17 - 22
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (366 KB) | HTML iconHTML

    A novel clock tree synthesis (CTS) method is proposed that improves the reliability of an integrated circuit system through reducing the peak current on the power/ground rails drawn by the clock tree buffers. The proposed CTS method entails the integration of XOR gates at one level of the clock tree to enable polarity assignment for peak current reduction. Unlike previous polarity assignment metho... View full abstract»

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  • A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells

    Publication Year: 2010, Page(s):23 - 28
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB) | HTML iconHTML

    Nowadays, design issues related to physical design and scalability are becoming the main bottlenecks of modern tools for technology mapping, limiting the usage of large cells. On the other hand, the generation of regular macro cells, such as compound gates, are becoming interesting from the manufacturing point of view, but they need to be properly integrated into the existing industrial design flo... View full abstract»

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  • A BDD-Based Design of an Area-Power Efficient Asynchronous Adder

    Publication Year: 2010, Page(s):29 - 34
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (627 KB) | HTML iconHTML

    Asynchronous system design in recent years has reemerged as an important vehicle in the field of high performance, low power and secure computing. On the other hand Binary Decision Diagrams (BDDs) have found significant applications for many years in the design, synthesis, verification, and testing of VLSI circuits. In this paper we have presented the design of a hybrid Domino PTL-CMOS based 2-bit... View full abstract»

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  • Efficient Hardware Looping Units for FPGAs

    Publication Year: 2010, Page(s):35 - 40
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (223 KB) | HTML iconHTML

    Looping operations impose a significant bottleneck to achieving better computational efficiency for embedded applications. To confront this problem in embedded computation either in the form of programmable processors or FSMD (Finite-State Machine with Datapath) architectures, the use of customized loop controllers has been suggested. In this paper, a thorough examination of zero-cycle overhead lo... View full abstract»

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  • Exploration of 2D Cellular Automata as Binary Sequence Generators

    Publication Year: 2010, Page(s):41 - 45
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (277 KB) | HTML iconHTML

    In this work a comprehensive exploration of Binary Sequence Generators (BSG) is offered, focusing on an alternative type of BSG (radix-2 counter) presenting low design complexity and interesting speed characteristics, based on 2D Cellular Automata (CA). Various “seed” configurations are explored and two architectures are examined, defining the most appropriate CA in terms of speed, s... View full abstract»

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  • Fine-Grained Fault Tolerance for Process Variation-Aware Caches

    Publication Year: 2010, Page(s):46 - 51
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (239 KB) | HTML iconHTML

    Continuous scaling in CMOS fabrication process makes circuits more vulnerable to process variations, which results in variable delay, malfunctioning, and/or leaky circuits. Caches are one of the biggest victims of process variations due to their large sizes and minimal cell features. To mitigate the impacts of process variations on caches, we propose to localize the effects of process variations a... View full abstract»

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  • Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT

    Publication Year: 2010, Page(s):52 - 57
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB) | HTML iconHTML

    Modular and hierarchical based test architecture are the two of the most common testing techniques used in complex SoC designs. However, modular test architectures uses an expensive (in terms of silicon area) test wrapper around each block. On the other hand hierarchical test architecture requires additional effort at block level to isolate each block from surrounding blocks and a TAM to perform s... View full abstract»

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  • Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA

    Publication Year: 2010, Page(s):58 - 62
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (197 KB) | HTML iconHTML

    In order to increase reliability and availability of Static-RAM based field programmable gate arrays (SRAM-based FPGAs), several methods of tolerating defects and permanent faults have been developed and applied. These methods are not well adapted for handling high fault rates for SRAM based FPGAs. In this paper, both single and double faults affecting configurable logic blocks (CLBs) are addresse... View full abstract»

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  • Self-Freeze Linear Decompressors for Low Power Testing

    Publication Year: 2010, Page(s):63 - 68
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB) | HTML iconHTML

    Even though linear decompressors constitute a very effective solution for compressing test data, they cause increased shift power dissipation during scan testing. Recently, a new linear decompression architecture was proposed which offers reduced shift power at the expense however of increased test data volume and test sequence length. In this paper we present a new linear encoding method which of... View full abstract»

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  • Logical Core Algorithm: Improving Global Placement

    Publication Year: 2010, Page(s):69 - 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (334 KB) | HTML iconHTML

    This work introduces a new technique to improve the global placement, which can be applied to any regular placer. We propose an algorithm called Logical Core, based on Google PageRanka®, which distributes probability weights to every cell in the circuit netlist. Then, these weights are used to select the most important cells for the global placement. By using this information, we... View full abstract»

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  • Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications

    Publication Year: 2010, Page(s):74 - 79
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (751 KB) | HTML iconHTML

    This paper proposes a new solution dealing with functional safety in safety critical applications, especially with concern to the second edition of the standard IEC 61508. Actually, this new edition defines quite stringent requirements for the on-chip redundancy, such that its use in FPGAs may be compromised. Based on a previous study, which presents an on-chip coarse grained mixed-signal Triple M... View full abstract»

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