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VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on

Date 5-7 July 2010

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Displaying Results 1 - 25 of 119
  • [Front cover]

    Page(s): C1
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  • [Title page i]

    Page(s): i
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  • [Title page iii]

    Page(s): iii
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  • [Copyright notice]

    Page(s): iv
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  • Table of contents

    Page(s): v - xiii
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  • Message from General Chairs

    Page(s): xiv
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  • Organizing Committee

    Page(s): xv - xvi
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  • Program Committee

    Page(s): xvii - xviii
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  • European ICT Research: 2011-2012 Outlook for Components and Systems

    Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (157 KB) |  | HTML iconHTML  

    In 2011-2012, the European ICT research priorities are focused on a set of Challenges with mid-to-long term goals that require trans-national collaboration. Each Challenge is addressed through a limited set of objectives that form the basis for Calls for Proposals and lead to EU-funded research projects. One of the Challenges addresses "Alternative Paths to Components and Systems", it covers nanoelectronic devices and components, photonics, integrated micro/nanosystems, multicore computing systems and embedded systems. View full abstract»

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  • Digital Microfluidic Biochips: A Vision for Functional Diversity and More Than Moore

    Page(s): 3 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB) |  | HTML iconHTML  

    Microfluidics-based biochips are revolutionizing high-throughput sequencing, parallel immunoassays, clinical diagnostics, and drug discovery. These devices enable the precise control of nanoliter volumes of biochemical samples and reagents. Compared to conventional laboratory procedures, which are cumbersome and expensive, miniaturized biochips offer the advantages of higher sensitivity, lower cost due to smaller sample and reagent volumes, system integration, and less likelihood of human error. This keynote paper provides an overview of droplet-based “digital” microfluidics and outlines emerging computer-aided design (CAD) tools for the automated synthesis and optimization of biochips from bioassay protocols. View full abstract»

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  • Small Worlds: The Dynamics of NoCs in Tomorrow SoC Architecture

    Page(s): 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (122 KB) |  | HTML iconHTML  

    Consumer electronics (CEs) is mainly characterized by its heterogeneity in products and markets. Moreover, large companies like Google, YouTube, Myspace, are revolutionizing the way to provide information contents. Today, several new CE devices have been introduced in the marketplace for receiving, visualizing, communicating, creating, and sending information. This changing implies that end-users are looking for devices with more features, better quality and elegant and simple user interface. This trend has a big impact on the features that System-on-Chips (SoC) have to support. View full abstract»

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  • Reconfigurable Architectures for Bioinformatics Applications

    Page(s): 6 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    Reconfigurable technology offers great advantages in bioinformatics applications vs. general-purpose computing. The presentation outlined in this paper looks into the attributes of several bioinformatics algorithms which make them suitable for reconfigurable computing, the resulting architectures, and their performance tradeoffs vs. general-purpose computers, graphics processor units (GPU) and VLSI. View full abstract»

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  • Challenges and Perspectives of Computer Architecture at the Nano Scale

    Page(s): 8 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    Advances in nanotechnology and the research of new materials has led to the elaboration of nano-components with novel properties and functions. Exploring how those novel components could be used to devise future computer architectures, complementing rather than supplementing CMOS technology, is a new research subject known as Nanocomputing. In this talk we will present the major challenges of such a research, the potential benefits of using technologies other than CMOS and some perspectives in terms of design and applications. We will illustrate the topic by presenting some of the most advanced results in the field, focusing on results from the European project FP7, NABAB, that explores how to build neuro-inspired computing structures with a variety of nanotechnologies. View full abstract»

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  • SUT-RNS Forward and Reverse Converters

    Page(s): 11 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (389 KB) |  | HTML iconHTML  

    Stored Unibit Transfer (SUT) has been recently proposed as a redundant high-radix encoding for the channels of a Residue Number System (RNS) that can improve the efficiency of conventional redundant RNS. In this paper we propose modulo 2n±1 forward and reverse converters for the SUT-RNS encoding. The proposed converters are based on parallel-prefix binary or modulo adders and are therefore very efficient. View full abstract»

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  • Clock Tree Synthesis with XOR Gates for Polarity Assignment

    Page(s): 17 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (366 KB) |  | HTML iconHTML  

    A novel clock tree synthesis (CTS) method is proposed that improves the reliability of an integrated circuit system through reducing the peak current on the power/ground rails drawn by the clock tree buffers. The proposed CTS method entails the integration of XOR gates at one level of the clock tree to enable polarity assignment for peak current reduction. Unlike previous polarity assignment methods, the skew of the generated clock tree with XORs is preserved as the physical layout of the clock tree is preserved during the polarity assignment process. Furthermore, the proposed clock tree permits the implementation of most of the previous polarity assignment methods through configurability of the control input of the XOR gates. Experimental results show that the peak current on the power/ground rails of the clock tree is reduced by an average of 55.2% without any degradation in the original clock skew. View full abstract»

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  • A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells

    Page(s): 23 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB) |  | HTML iconHTML  

    Nowadays, design issues related to physical design and scalability are becoming the main bottlenecks of modern tools for technology mapping, limiting the usage of large cells. On the other hand, the generation of regular macro cells, such as compound gates, are becoming interesting from the manufacturing point of view, but they need to be properly integrated into the existing industrial design flows. In this paper, we present an efficient methodology for identifying the cells that can extend an existing standard-cell library. We validated our approach on different benchmarks targeting area minimization and we also analyzed timing, power consumption and routing effects for the final circuit implementation. View full abstract»

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  • A BDD-Based Design of an Area-Power Efficient Asynchronous Adder

    Page(s): 29 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (627 KB) |  | HTML iconHTML  

    Asynchronous system design in recent years has reemerged as an important vehicle in the field of high performance, low power and secure computing. On the other hand Binary Decision Diagrams (BDDs) have found significant applications for many years in the design, synthesis, verification, and testing of VLSI circuits. In this paper we have presented the design of a hybrid Domino PTL-CMOS based 2-bit asynchronous adder, the PTL part of which is designed using the principles of BDD. The designed asynchronous adder has been implemented for 32-bit and the simulation results indicate a reduction of 16% in number of transistors, 8% in power and 21% in power-delay-area-product over earlier reported results without any compromise in the delay. The implementation has been done using UMC 180nm, 1.5V technology. View full abstract»

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  • Efficient Hardware Looping Units for FPGAs

    Page(s): 35 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (223 KB) |  | HTML iconHTML  

    Looping operations impose a significant bottleneck to achieving better computational efficiency for embedded applications. To confront this problem in embedded computation either in the form of programmable processors or FSMD (Finite-State Machine with Datapath) architectures, the use of customized loop controllers has been suggested. In this paper, a thorough examination of zero-cycle overhead loop controllers applicable to perfect loop nests operating on multi-dimensional data is presented. The design of such loop controllers is formalized by the introduction of a hardware algorithm that fully automates this task for the spectrum of behavioral as well as generated register-transfer level architectures. The presented algorithm would prove beneficial in the field of high-level synthesis of architectures for data-intensive processing. It is also shown that the proposed loop controllers can be efficiently utilized for supporting generalized loop structures such as imperfect loop nests. The performance characteristics (cycle time, chip area) of the proposed architectures have been evaluated for FPGA target implementations. It is shown that maximum clock frequencies of above 230MHz with low logic footprints of about 1.4% of the overall logic resources can be achieved for supporting up to 8 nested loops with 16-bit indices on a modestly-sized Xilinx Virtex-5 device. View full abstract»

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  • Exploration of 2D Cellular Automata as Binary Sequence Generators

    Page(s): 41 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (277 KB) |  | HTML iconHTML  

    In this work a comprehensive exploration of Binary Sequence Generators (BSG) is offered, focusing on an alternative type of BSG (radix-2 counter) presenting low design complexity and interesting speed characteristics, based on 2D Cellular Automata (CA). Various “seed” configurations are explored and two architectures are examined, defining the most appropriate CA in terms of speed, silicon area and power dissipation. View full abstract»

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  • Fine-Grained Fault Tolerance for Process Variation-Aware Caches

    Page(s): 46 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    Continuous scaling in CMOS fabrication process makes circuits more vulnerable to process variations, which results in variable delay, malfunctioning, and/or leaky circuits. Caches are one of the biggest victims of process variations due to their large sizes and minimal cell features. To mitigate the impacts of process variations on caches, we propose to localize the effects of process variations at a word level, not at the conventional cache set, cache way, or cache line level. Faulty words are disabled or shut down completely and accesses to those words are bypassed to a small set of word-length buffers. This technique is shown to be effective in reducing performance penalty due to process variations and in increasing the parametric yield up to 90% when subjected to the performance constraints. View full abstract»

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  • Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT

    Page(s): 52 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (322 KB) |  | HTML iconHTML  

    Modular and hierarchical based test architecture are the two of the most common testing techniques used in complex SoC designs. However, modular test architectures uses an expensive (in terms of silicon area) test wrapper around each block. On the other hand hierarchical test architecture requires additional effort at block level to isolate each block from surrounding blocks and a TAM to perform scan compression. In this paper, we analyze the limitations of the modular test architecture. Based on the analysis, we propose a test plan for hierarchical test architecture by integrating partition chain, combinational scan compression and (RPCT) reduced pin count test. Experimental results show that approximately 50% of DFT area can be reduced using the partition chain as compared to standard test wrapper. It also demonstrates the feasibility of the proposed test plan using a commercial ATPG tool. View full abstract»

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  • Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA

    Page(s): 58 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (197 KB) |  | HTML iconHTML  

    In order to increase reliability and availability of Static-RAM based field programmable gate arrays (SRAM-based FPGAs), several methods of tolerating defects and permanent faults have been developed and applied. These methods are not well adapted for handling high fault rates for SRAM based FPGAs. In this paper, both single and double faults affecting configurable logic blocks (CLBs) are addressed. We have developed a new fault-tolerance technique that capitalizes on the partial reconfiguration capabilities of SRAM-based FPGA. The proposed fault-tolerance method is based on triple modular redundancy (TMR) combined with master-slave technique, and exploiting partial reconfiguration to tolerate permanent faults. Simulation results on reliability improvement corroborate the efficiency of the proposed method and prove that it compares favorably to previous methods. View full abstract»

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  • Self-Freeze Linear Decompressors for Low Power Testing

    Page(s): 63 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (446 KB) |  | HTML iconHTML  

    Even though linear decompressors constitute a very effective solution for compressing test data, they cause increased shift power dissipation during scan testing. Recently, a new linear decompression architecture was proposed which offers reduced shift power at the expense however of increased test data volume and test sequence length. In this paper we present a new linear encoding method which offers both high compression and low shift power dissipation at the same time. A new low-cost, test-set-independent scheme is also proposed which can be combined with any linear decompressor for reducing the shift power during testing. Extensive experiments show that the proposed method offers reduced test power dissipation, test sequence length and test data volume at the same time, with very small area requirements. View full abstract»

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  • Logical Core Algorithm: Improving Global Placement

    Page(s): 69 - 73
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    This work introduces a new technique to improve the global placement, which can be applied to any regular placer. We propose an algorithm called Logical Core, based on Google PageRanka®, which distributes probability weights to every cell in the circuit netlist. Then, these weights are used to select the most important cells for the global placement. By using this information, we are able to improve global placement in terms of wirelength. The Logical Core algorithm proposes a new complexity rule to the placement graph. This complexity has a great similarity with the Rent's Rule. The technique improves the total wirelength in all tested cases by 4.5%. View full abstract»

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  • Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications

    Page(s): 74 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (751 KB) |  | HTML iconHTML  

    This paper proposes a new solution dealing with functional safety in safety critical applications, especially with concern to the second edition of the standard IEC 61508. Actually, this new edition defines quite stringent requirements for the on-chip redundancy, such that its use in FPGAs may be compromised. Based on a previous study, which presents an on-chip coarse grained mixed-signal Triple Modular Redundancy architecture in FPGAs, this paper proposes a method to implement on-chip redundancy in FPGAs which complies with the new edition of the standard. Firstly, the paper will discuss the standard, thereafter the rules and constraints for the implementation of the on-chip redundancy, and finally it will evaluate the compliance of the method and suggest some improvements. The paper shows that the use of on-chip redundancy for FPGAs is achievable. View full abstract»

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