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Industrial Embedded Systems (SIES), 2010 International Symposium on

Date 7-9 July 2010

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Displaying Results 1 - 25 of 38
  • [Title page]

    Publication Year: 2010 , Page(s): 1 - 3
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    Freely Available from IEEE
  • [Front matter]

    Publication Year: 2010 , Page(s): i - v
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  • Committees

    Publication Year: 2010 , Page(s): vi - vii
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    Freely Available from IEEE
  • Welcome to SIES 2010

    Publication Year: 2010 , Page(s): viii
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    Freely Available from IEEE
  • Inferring energy and performance cost of RTOS in priority-driven scheduling

    Publication Year: 2010 , Page(s): 1 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB) |  | HTML iconHTML  

    We present a high-level method for rapidly and accurately estimating energy and performance cost of Real-Time Operating Systems. We investigate priority-driven scheduling and assume inter-dependent tasks competing for shared resources. Unlike most other approaches, which rely on Transaction-Level Modeling (TLM), we infer the information we need directly from executing the algorithmic specification, without needing to build any high-level architectural model. We distinguish two main components in our approach: first, an accurate one-time pre-characterization of the main RTOS functionalities in terms of energy and cycles; second, the development of an algorithm to rapidly predict the occurrences of such RTOS functionalities. Finally, we validate our approach by comparing it against gate level for accuracy and against TLM for speed. We obtain a worst-case error of 12% against a mean speedup of ~30X. View full abstract»

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  • Optimizing hierarchical schedules for improved control performance

    Publication Year: 2010 , Page(s): 9 - 17
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB) |  | HTML iconHTML  

    Embedded control systems typically consist of several control loops, with different parts of each control application being mapped onto different processors that communicate over one or more communication buses. In such setups, the system architecture and scheduling policies have a significant impact on control performance. In this paper we show how to optimally choose the parameters of hierarchical schedules on the communication bus in order to improve multiple control performance metrics. View full abstract»

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  • A comparison of Linux CAN drivers and their applications

    Publication Year: 2010 , Page(s): 18 - 27
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (569 KB) |  | HTML iconHTML  

    The aim of this paper is to introduce LinCAN, a CAN driver system for Linux, developed at the Department of Control Engineering of the Czech Technical University in Prague, and to provide a thorough comparison with SocketCAN, which is the most common CAN solution for Linux nowadays. Thorough timing analysis and performance comparison with Socket CAN are presented, with several case-studies and applications of LinCAN shown in the end. LinCAN has been developed since 2003 and supports many CAN controllers from various manufacturers. It is designed with emphasis on strict real-time properties and reliability, making it ideally suitable for networked control systems (as is also demonstrated in the case-studies). LinCAN is also portable to other Operating Systems and can be used even system-less (without any OS) on less-powerful microcontrollers. A timing analysis and performance tests of both drivers were performed using various types of load with several recent Linux kernels. Obtained results indicate that LinCAN seems better suited for hard real-time applications, its performance being either better or on-par with SocketCAN in presented tests. Both LinCAN and SocketCAN drivers are completely open-source as well as our testing tools, so any researcher interested in our results is welcome to download all relevant source codes, check our testing methodology in detail and perhaps recreate our results or extend them by performing other test, providing valuable feedback and independent verification of our work. View full abstract»

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  • Verification of a CAN bus model in SystemC with functional coverage

    Publication Year: 2010 , Page(s): 28 - 35
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (447 KB) |  | HTML iconHTML  

    Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which is a challenging task for the verification engineer. To cope with complexity, verification techniques working on different abstraction levels are best practice. SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of functional coverage. In this paper we present a functional coverage library that implements parts of the IEEE 1800-2005 SystemVerilog standard and allows capturing functional coverage throughout the design and verification process with SystemC. Moreover, we will demonstrate the usability of the approach with a case study working on a CAN bus model written in SystemC. View full abstract»

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  • Compressive sensing optimization over ZigBee networks

    Publication Year: 2010 , Page(s): 36 - 44
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB) |  | HTML iconHTML  

    Efficient data aggregation and compression in sensor networks is becoming fundamental with the increase of the number of nodes in the network. Although several data aggregation and compression techniques have been proposed in the literature only few of them can perform in-network compression and can extend lifetime without prior knowledge of the sensed data or without a central coordination. In this paper we consider a scenario where a wireless sensor network (WSN) exploits ZigBee protocols for smart building application. We study a classical gathering scheme and a distributed compressive sampling approach. We discuss limitations and we propose a new distributed mixed algorithm for in-network compression. With this algorithm each node takes a decision about which scheme to adopt aiming at the reducing the number of packets to transmit. We are interested in scalability of this new method and lifetime of the system with respect to the increase of network dimension. Simulations are performed using real data sets and results show that the use of this algorithm permits to obtain longer network lifetime with small computational complexity. The performances of the algorithm are also investigated when some sensor parameters are modified and sporadic readings rise in the network. View full abstract»

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  • An innovative frequency hopping management mechanism for Bluetooth-based industrial networks

    Publication Year: 2010 , Page(s): 45 - 50
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    This paper presents a novel frequency hopping management mechanism for Bluetooth networks used in industrial environments. In these contexts, time-critical transmissions have to be supported by the automation network. Transmission timeliness can be compromised by interference between co-located cells, that increases the delay because of retransmissions. The paper introduces a novel mechanism, called a Piconet Management Approach, based on an innovative frequency hopping methodology which reduces the interference among co-located piconets, thus improving the network performance in terms of transmission delay and throughput. The paper describes the approach and discusses its performance. View full abstract»

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  • Scratch detector–A FPGA based system for scratch detection in industrial picture development

    Publication Year: 2010 , Page(s): 57 - 62
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB) |  | HTML iconHTML  

    This paper presents a complete system to detect scratches in rolls of photo paper. The idea is to use a group of white LED to illuminate the picture and highlight the scratches only. The system mainly consists of a camera to obtain images from the paper and an Altera DE2-70 FPGA Board to process those images. We can show that observing the scratches by applying specific filters on the acquired image makes the detection very simple and reliable. View full abstract»

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  • Implementation of a bumpless switch in axial magnetic bearings

    Publication Year: 2010 , Page(s): 63 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    In this work, hardware and software issues of building a control system for axial magnetic bearings are considered. The third generation of magnetic bearings requires self-tuning and self-calibration. These techniques should be complemented by an option of a controller switch in operational processes. An implementation of a bumpless method is discussed for cases that solve the problem of system instability and signal overshoot during switching. View full abstract»

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  • A semi-active suspension embedded controller in a FPGA

    Publication Year: 2010 , Page(s): 69 - 78
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (735 KB) |  | HTML iconHTML  

    This paper explores the applicability of a Piece-Wise Multilinear Fuzzy Inference System (PWM-FIS) to the realization of embedded digital controllers for semi-active suspension systems. The nonlinear controller, obtained by approximation of a modified Skyhook control strategy trough off-line training of the PWM-FIS, has been implemented in a Field Programmable Gate Array (FPGA) following a hardware-software partition methodology. The system comprehends four three-input/one-output parallel fuzzy controllers, thus allowing its application to the control of a complete four-wheel vehicle suspension system. Obtained input/output latency (control signal skew) of the implemented controller is only 90ns which warrants its applicability to any suspension system with high-speed real-time advanced control requirements. View full abstract»

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  • Distributed coordination of task migration for fault-tolerant FlexRay networks

    Publication Year: 2010 , Page(s): 79 - 87
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (473 KB) |  | HTML iconHTML  

    In this paper we present an approach to increase the fault tolerance in FlexRay networks by introducing backup nodes to replace defect ECUs (Electronic Control Units). In order to reduce the memory requirements of such backup nodes, we distribute redundant tasks over different nodes and propose the distributed coordinated migration of tasks of the defect ECU to the backup node at runtime. This approach enhances our former work in, where we extended the FlexRay bus schedule by redundant slots to consider changes in the communication/slot assignment and investigated and evaluated different solutions to migrate the redundant tasks to the backup node using the static and/or dynamic segment of the communication cycle for transmissions. We present the approach of distributed coordination for migration and communication instead of additional dedicated coordinator nodes to further increase the fault tolerance. With this approach we improve the safety of FlexRay networks by avoiding a possible single point of failure due to a dedicated coordinator node also minimizing the necessary time needed for a reconfiguration after an ECU failure. Furthermore, we reduce the overhead within the communication and the demand for additional hardware components. View full abstract»

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  • HILAC: A framework for hardware in the loop simulation and multi-platform automatic code generation of WSN applications

    Publication Year: 2010 , Page(s): 88 - 97
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (550 KB) |  | HTML iconHTML  

    Hardware and software platforms for Wireless Sensor Networks (WSNs) are almost as diverse as their application areas, with very limited standardization. Moreover, heterogeneous programming abstractions put high barrier in application development and there is hardly any support for application debugging, except for a few blinking LEDs. Similar problems have been solved in application domains that have similar cost constraints, such as automotive, by the use of model-based design. We address the lack of model-based design tools for the WSN domain by providing a framework (based on Simulink, Stateflow and Stateflow Coder) in which an application developer can model a WSN application by using Stateflow constructs and then use a single model to perform multi-platform Hardware-In-the-Loop (HIL) simulation and platform-specific application code generation. View full abstract»

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  • VHDL observers for clock constraint checking

    Publication Year: 2010 , Page(s): 98 - 107
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    Logical time has proved very useful to model heterogeneous and concurrent systems at various abstraction levels. The Clock Constraint Specification Language (CCSL) uses logical clocks as first-class citizens and supports a set of (logical) time patterns to specify the time behavior of systems. We promote here the use of CCSL to express and verify safety properties of VHDL designs. Our proposal relies on an automatic transformation of a CCSL specification into VHDL code that checks the expected properties. Being written in VHDL this code can be integrated in a classical VHDL design and verification flow. Our proposed structural transformation assembles instances of pre-built VHDL components while preserving the polychronous semantics of CCSL. This is not trivial due to major differences between the discrete-time delta cycle based semantics of VHDL and the fixed point semantics of CCSL. This paper describes these differences and proposes solutions to deal with them so as to build VHDL observers for the kernel CCSL constraints. We illustrate the approach by verifying an open-source implementation of the AMBA AHB-to-ABP bridge. View full abstract»

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  • Automated conflict-free distributed implementation of component-based models

    Publication Year: 2010 , Page(s): 108 - 117
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (209 KB) |  | HTML iconHTML  

    We propose a method for generating distributed implementations from high-level models expressed in terms of a set of components glued by rendezvous interactions. The method is a 2-phase transformation preserving all functional properties. The first phase is a source-to-source transformation from global state to a partial state model (to relax atomicity). This transformation replaces multi-party rendezvous interactions by send/receive primitives managed by a set of automatically generated distributed schedulers. These schedulers are conflict-free by construction in the sense that they do not require communication in order to safely execute interactions of the highlevel model. In the second phase, from the transformed model in phase one, we generate C++ distributed code using either TCP sockets or MPI to implement send/receive primitives. Our method is fully implemented in a tool for automatic generation of distributed applications. We present experimental results using different case studies. View full abstract»

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  • A system for synthesizing abstraction-enabled simulators for binary code verification

    Publication Year: 2010 , Page(s): 118 - 127
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    Formal verification of embedded software is crucial in safety-critical applications, ideally requiring as little human intervention as possible. Binary code model checking based on hardware simulators already comes close to this goal, although with high initial effort for developing a simulator of the respective target platform. In the embedded systems domain with its varieties of different architectures in use, this can severely restrict the applicability of this approach. To remedy this drawback, we describe a system for automatically synthesizing simulators, which are suited for model checking in that they support automatic abstraction. We evaluate the practicality of this approach by synthesizing simulators for the Atmel ATmega16 and Intel MCS-51 microcontrollers. View full abstract»

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  • Usage of the safety-oriented real-time OASIS approach to build deterministic protection relays

    Publication Year: 2010 , Page(s): 128 - 135
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (501 KB) |  | HTML iconHTML  

    As any safety-related system, medium voltage protection relays have to comply with a Safety Integrated Level (SIL), as defined by the IEC 61508 standard. The safety-function of the software part of protection relays is first to detect any faults within the supervised power network, then ask the tripping of the circuit breakers in order to isolate the faulty portion of the network. However, it is required that detection and isolation of faults must occur within a given time, as specified by the IEC 60255 standard. Schneider Electric currently achieves the demonstration that a protection relay is performing its safety-function within such temporal constraints at the price of a costly phase of tests. The OASIS approach is a complete tool-chain to build safety-critical deterministic real-time systems, which enables the demonstration of the system timeliness. In this paper, we show how we apply the OASIS approach to build a deterministic protection relay system. We designed a software platform called OASISepam, based on an existing product from Schneider Electric, namely the Sepam 10. We show a preliminary evaluation of our implementation over a STR710 ARM-based board that runs the OASIS kernel. Notably, we show that the observed worst-case end-to-end detection time of OASISepam fulfils the specified constraint expressed in the design phase and translated in the OASIS programming model. Consequently, the temporal behaviour of protection relays is mastered, thus reducing application development costs and allowing the optimization of selectivity. View full abstract»

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  • An exception based approach to timing constraints violations in real-time and multimedia applications

    Publication Year: 2010 , Page(s): 136 - 145
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (218 KB) |  | HTML iconHTML  

    In this paper, an exception-based programming paradigm is envisioned to deal with timing constraints violations occurring in soft real-time and multimedia applications written in the C language. In order to prove viability of the approach, a mechanism allowing to use such paradigm has been designed and implemented as an open-source library of C macros making use of the standard POSIX API (a few Linux-specific optimizations are also briefly discussed). The envisioned approach has been validated by modifying mplayer, one of the most widely used multimedia player for Linux, so as to use the introduced library. Experimental results demonstrate how the exception-based paradigm is effective in improving the audio/video delay exhibited by the player. View full abstract»

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  • Enhancing reliability in IEEE 802.11 based real-time networks through transport layer retransmissions

    Publication Year: 2010 , Page(s): 146 - 155
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (314 KB) |  | HTML iconHTML  

    As the number of application areas for wireless technologies grows, the need for providing both predictable and reliable communication over wireless networks becomes apparent. Cooperative embedded systems for industrial automation are one example of systems with these needs. Previously, we developed a framework for reliable real-time communication in a single-hop wireless network with a logical star topology. The framework was placed on top of IEEE 802.15.4 and combines transport layer retransmissions with real-time analysis admission control. IEEE 802.15.4 was selected due to its advantageous energy saving techniques, making it an interesting choice for wireless sensor networks in industrial contexts. However, its achievable data rate is rather low, especially when voice or video for industrial surveillance and monitoring need to be transferred. Hence, we adapt our framework to fit the IEEE 802.11 standard and evaluate its performance using a data traffic model from industrial control and surveillance systems. The performance of the framework is evaluated in terms of network utilization, message error rate and delay distribution using theoretical analysis as well as computer simulations. View full abstract»

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  • An energy-aware algorithm for TDMA MAC protocols in real-time wireless networks

    Publication Year: 2010 , Page(s): 156 - 165
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB) |  | HTML iconHTML  

    In distributed embedded systems operated by battery, energy management is a critical issue that has to be addressed at different architecture levels. For systems that tightly interact with the environment, an additional goal is to enforce a set of real-time constraints to guarantee a desired performance. A lot of research has focused on power management at the communication level, especially for MAC protocols. However, not many authors considered both real-time and energy requirements in wireless communication systems. In this paper we present El-MAC, an elastic energy-aware algorithm at the MAC level for wireless distributed systems with real-time constraints. Under this framework, each node can adapt its bandwidth requirements to balance performance versus energy consumption, taking both lifetime and message deadlines into account. We describe the algorithm for a generic TDMA MAC protocol. View full abstract»

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  • An energy saving criterion for wireless sensor networks with time synchronization requirements

    Publication Year: 2010 , Page(s): 166 - 173
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB) |  | HTML iconHTML  

    In Wireless Sensor Networks (WSNs) time synchronization is essential to aggregate and to process data collected by different nodes, both in real-time and off-line. However, time synchronization protocols at the application layer may significantly increase the amount of dissipated power. This paper analyzes this problem and suggests a communication scheme as well as a criterion to reduce the power consumption of WSN nodes, while preserving communication reliability and meeting target synchronization accuracy requirements. View full abstract»

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  • A component-based architecture for adaptive bandwidth allocation in Wireless Sensor Networks

    Publication Year: 2010 , Page(s): 174 - 183
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    In this paper we investigate the problem of reactive on-line bandwidth allocation in adaptive Wireless Sensor Networks. In adaptive WSN for monitoring applications, nodes can react to physical events by adapting their behavior, for instance increasing the amount of computation to be performed, or reducing the amount of consumed energy. Accordingly, the nodes may increase or decrease their bandwidth requirements. Hence, a reconfiguration algorithm is needed to reallocate the bandwidth to the different nodes, to maximize a certain global quality index. To address this problem, we first present a component-based methodology to model nodes and cluster of nodes as components. Then, we use this methodology to decompose the global optimization problem into simpler local problems, so to enable the design of scalable heuristic algorithms. We propose two different heuristic algorithms, and we compare their performance by extensive simulations against a global optimization procedure based on the Simplex algorithm. We demonstrate that our proposed heuristics perform very well under almost all circumstances. View full abstract»

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  • Improving the tests coverage of a medium voltage protection device using system simulation approaches

    Publication Year: 2010 , Page(s): 184 - 187
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB) |  | HTML iconHTML  

    In this paper we focus on improving the tests coverage of a Schneider Electric protection device using system modeling and simulation techniques. Our approach consists of modeling the device in its operating environment: Timed Transaction Level Models (T-TLM) for the digital parts, Matlab waveforms for the analog parts, and scripting language for the tests automation. This approach is applied on a medium voltage protection relay called Sepam10. This example is considered to be typical for a wide class of protection and safety devices at Schneider Electric, thus showing that the modeling approaches used in high complexity System On Chip (SoC) devices are also of great interest for power electronic control devices. View full abstract»

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