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Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on

Date 1-4 Aug. 2010

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Displaying Results 1 - 25 of 322
  • Welcome to the 53rd IEEE international Midwest Symposium on Circuits and Systems (MWSCAS 2010)

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  • General information

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  • MWSCAS 2010 organizing committee

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  • [Copyright notice]

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  • Table of contents

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  • Author index

    Page(s): 1 - 18
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  • Emerging non-volatile memory technologies: From materials, to device, circuit, and architecture

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1440 KB) |  | HTML iconHTML  

    The emerging nonvolatile memory technologies are gaining significant attentions from semiconductor in recent years. Multiple promising candidates, such as phase change memory, magnetic memory, resistive memory, and memristor, have gained substantial attentions and are being actively pursued by industry. In this paper, we will give a 360 degree introduction on emerging non-volatile memory technologies by using spin-transfer torque random access memory (STT-RAM) as an example. The discussion includes process technology, device modeling, design considerations, and architecture in future computing systems. View full abstract»

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  • Model study of 1T-1STT MTJ memory arrays for embedded applications

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (934 KB) |  | HTML iconHTML  

    The use of current to switch nanomagnets has opened up opportunities for using spin-torque-transfer (STT) based magnetic memories in embedded applications. This paper presents a design space exploration of 1T-1STT MTJ arrays for embedded applications, under variations and disturbs conditions. View full abstract»

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  • Yield modeling and assessment for nanocrossbar systems

    Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (674 KB) |  | HTML iconHTML  

    Crossbar architectures are promising in the emerging nanoelectronic environment, yet suffer from massive defects. Defect-tolerant logic mapping emerges as a new challenging process in constructing nanocrossbar-based architectures. New yield models and metrics need to be developed to evaluate the logic mapping process, due to the complexity involved in searching for a valid mapping. We show the traditional concept of yield becomes unrealistic due to the lack of consideration for runtime cost, and present a new mapping-aware yield model. Furthermore, we provide assessment of defect-tolerant logic mapping from the perspective of mismatch number distribution. It turns out that such mismatch number distribution serves as a solid basis on understanding the various new factors involved in the logic mapping process. View full abstract»

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  • Intel LVS logic in CNT technology

    Page(s): 13 - 16
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    In this paper, we systematically evaluate combinational logic families for CNT technology implementation for a variety of logic families, signal transition times, and transistor parameters. We compare CMOS static logic, and Intel LVS logic in CNT and silicon technologies by SPICE simulation based on Predictive Technology Model and Stanford compact CNFET models. We observe that CMOS static logic in CNT technology achieves limited (e.g., 3.44×) performance improvement and (e.g., 3.83×) power consumption reduction, while Intel LVS logic achieves more significant performance improvement and orders-of-magnitude of power consumption reduction. Intel LVS logic achieves an average of 4.02× performance improvement and 1137.64× power consumption reduction compared with CMOS static logic in silicon for the same combinational logic functions and input signals, and enhanced reliability, making it an ideal combinational logic circuit paradigm in CNT technology. View full abstract»

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  • Advancements on crossbar-based nanoscale reconfigurable computing Platforms

    Page(s): 17 - 20
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    A recently proposed carbon nanotube (CNT) crossbar nano-architecture provides the first purely CNT-based platform for nanoscale computing systems. In this paper, I present a number of degrees of freedom in optimizing this nano-architecture, and evaluate several variant nanoscale computing platforms based on a combination of floating-gate transistor arrays and programmable vias. Experimental results based on Stanford compact CNFET model show that proper device integration, cell granularity, and logic family (e.g., reconfigurable CMOS static logic in floating-gate transistor arrays) lead to an optimized nanoscale computing platform, with reduced manufacture complexity, improved logic density, improved performance, and reduced power consumption. View full abstract»

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  • Power-on-reset circuit with power-off auto-discharging path for passive RFID tag ICs

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (878 KB) |  | HTML iconHTML  

    A nano-power power-on-reset (POR) circuit for passive RFID tag is presented in this paper. It is applied to a passive UHF C1G2 RFID tag ICs fabricated in a 90-nm CMOS technology. Measurement results confirm that the generated POR pulse signal is accurate and reliable due to the proposed hysteresis-comparator structure and power-off auto-discharging path. Moreover, the POR circuit consumes 150-nA quiescent current only. View full abstract»

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  • A multi-rail shared error ADC with pipeline structure for DC-DC converter digital controller in 0.13µm CMOS technology

    Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1348 KB) |  | HTML iconHTML  

    This paper presents the design and measurement results of an error ADC with a pipeline structure for DC-DC converter digital controller in 0.13μm technology. The proposed error ADC shared by three voltage rails through an analog MUX. The error signal is amplified by a differential amplifier and a switched capacitor amplifier with a total gain of 10. The amplified error signal is then digitized with a conventional 5b pipeline ADC. The ADC operates at a sampling frequency of 12 MSPS, draws 3mA from a single 1.5V power supply with an area of 500μm by 600μm. Metal fringe capacitors are used for switched-capacitor circuit. View full abstract»

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  • A power effective 5-bit 600 MS/s binary-search ADC with simplified switching

    Page(s): 29 - 32
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    This paper proposes the design of a binary search ADC that uses two different techniques, namely, distributed-residue and folding. These can prevent signal dependent offset and reduce the switching network complexity. A 5-bit binary-search ADC applying such proposed techniques has been developed in 65 nm CMOS. It consumes 540 μW under 1V supply voltage at the operating frequency of 600 MS/s. The simulation results demonstrate that the design achieves a SNDR of 30.8 dB at Nyquist input frequency with a figure of merit (FOM) of 32 fJ/conversion-step. View full abstract»

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  • A fourth-order feedforward continuous-time delta-sigma ADC with 3MHz bandwidth

    Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1044 KB) |  | HTML iconHTML  

    A fourth-order feedforward continuous-time (CT) delta-sigma modulator is presented. The modulator takes an active-RC OpAmp as the first stage because of the high-linearity requirement, and the other three stages are composed by Gm-C integrators. In feedforward topology, a higher out-of-band NTF gain could be taken for better performance. As we know, the most important part in the feedforward CT ΔΣ modulator is the summation circuit for the feedforward paths. The modulator uses a tuning adder, which we propose, to make sure the modulator can work correctly even under the influence of the process variation on resistors. Finally, the delta-sigma modulator is implemented in standard digital 0.18-μm CMOS process, which achieves 57.84 dB SNDR over a 3MHz signal bandwidth at an OSR of 16.67. The power consumption of the CT delta-sigma modulator is 11.8 mW from the 1.8-V supply. View full abstract»

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  • SIDO buck converter with independent outputs

    Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1084 KB) |  | HTML iconHTML  

    The portable electronics market is rapidly migrating towards more compact devices requiring multiple high-integrity high-efficiency voltage supplies for empowering the systems. This paper demonstrates a single inductor used in a buck converter with two output voltages from an input battery with voltage of value 3V. The main target is low cross regulation between the two outputs to supply independent load current levels while maintaining desired output voltage values well within a ripple that is set by adaptive hysteresis levels. A reverse current detector to avoid negative current flowing through the inductor prevents efficiency degradation at light load. View full abstract»

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  • Static simulation: A method for power and energy estimation in embedded microprocessors

    Page(s): 41 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (409 KB) |  | HTML iconHTML  

    Current methodologies for software-level power and energy estimation use a microprocessor's power model combined with specialized tools that profile the program under study. These tools commonly rely on real-time program execution or simulations to gather the information needed, a process that usually requires a full set of real run-time data. This work proposes the use of static code simulation as an alternative to analyze and predict the program's behavior. This, in combination with a microprocessor's power model, allows to estimate power and energy with only a small amount of run-time data. Furthermore, the low execution time of the proposed method allows for its use as in iterative power optimizers. We present results obtained for a set of representative benchmark programs applied ran on a PowerPC 603e microprocessor. Power and energy estimates with mean absolute errors below 7% and 15%, respectively, are reported for the analyzed test cases. View full abstract»

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  • Analysis and implementation of Raptor codes on embedded systems

    Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (361 KB) |  | HTML iconHTML  

    Raptor codes have been proven very suitable for mobile multimedia content delivery, and yet they have not been analyzed in the context of embedded systems. At the heart of Raptor codes for binary erasure channel (BEC) is the matrix inversion operation. This paper analyzes the performance, energy profile and resource implication of two matrix inversion algorithms for the Raptor decoder on a system on a chip (SoC) platform with a soft-core embedded processor. We show how the cache size, matrix memory type and organization affect the two algorithms under consideration. View full abstract»

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  • A reconfigurable pattern matching hardware implementation using on-chip RAM-based FSM

    Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (534 KB) |  | HTML iconHTML  

    The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SoC) designs because of their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with embedded memory and processor blocks has further expanded the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying product requirements. In this paper, a reconfigurable hardware implementation for pattern matching using Finite State machine (FSM) is proposed. The FSM design is RAM-based and is reconfigured on the fly through altering memory contents only. An embedded processor is used for orchestrating run time reconfiguration. Experimental results show that the system can reconfigure itself based on a new incoming pattern and perform the text search without the need of a host processor. Results also proved that each search iteration was executed in one clock cycle and the maximum achievable clock frequency is independent of search pattern length. View full abstract»

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  • Increasing sleep-mode efficiency by reducing battery current using a DC-DC converter

    Page(s): 53 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (498 KB) |  | HTML iconHTML  

    Battery current is a key parameter that decides the runtime of a portable electronic system. For low power applications like IEEE 802.15.4 and Zigbee wireless network, the average battery current drain approximates the sleep mode current drain, since significantly more time is spent in sleep than in active usage. This paper proposes substituting a DC-DC converter for a low drop-out (LDO) regulator in the sleep mode power chain, such that the current drawn from the battery would be less than the actual current drained by the load. The battery current saving, and hence battery runtime extension, is estimated to be around 35% based on the analysis of a 65 nm CMOS IEEE 802.15.4/Zigbee low power wireless system-on-chip (SoC) model, whose parameters are extracted from state-of-the-art industrial products and experimental data from advanced nanometer processes. View full abstract»

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  • GPU accelerated elliptic curve cryptography in GF(2m)

    Page(s): 57 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (395 KB) |  | HTML iconHTML  

    This paper presents the Graphics Processing Unit (GPU) accelerated version of the LSB Invariant scalar point multiplication for binary elliptic curves. This method was implemented using the CUDA programming language for nVidia graphics cards. With a parallel factor of (length+1) and López-Dahab projective coordinate Pi's, on an nVidia GTX 285 graphics card precomputation takes 190.203995 ms while the actual scalar point multiplication takes 173.121002 ms for GF(2163). With a parallel factor of (length+1)*(length) and López-Dahab projective coordinate Pi's, on an nVidia GTX 285 graphics card precomputation of 2iP points takes 9.545 ms while the actual scalar point multiplication takes 10.743 ms (~93.0839 kP/s) for GF(2163). With a parallel factor of (length+1)*(length) and affine coordinate Pi's, on an nVidia GTX 285 graphics card precomputation takes 140.078003 ms for GF(2163) while the actual scalar point multiplication takes 10.363000 ms (~96.4972 kP/s) for GF(2163). View full abstract»

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  • Synthesizing optimal fixed-point arithmetic for embedded signal processing

    Page(s): 61 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (445 KB) |  | HTML iconHTML  

    Using fixed-point arithmetic rather than floating-point for data processing can significantly reduce the cost and power consumption of embedded systems. Unfortunately, this also shifts the burden of managing the data representation from run time to compile time, and in many cases the task of compile-time optimization must be done manually. A number of attempts have been made to formalize this process, and fixed-point methods have even been codified into an industry standard for a popular hardware-definition language, VHDL, in recent years. While the standard fixed-point libraries are certainly correct in the strict sense, they overlook an important practical consideration and may often produce results that are far from optimal. This paper discusses methods for maximizing the efficiency of fixed-point operations by careful use of the standard libraries. View full abstract»

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  • Bit-serial CORDIC: Architecture and implementation improvements

    Page(s): 65 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (454 KB) |  | HTML iconHTML  

    This paper presents a new and improved bit-serial CORDIC architecture. A detailed description of the bit-serial implementation and its Control Unit is presented. It is shown that the improvement is due to a reduction of registers in the implementation and is made possible by ensuring that the angular path is calculated prior to the corresponding vector paths. In addition, the improved architecture is implemented in VHDL and synthesized for a UMC 130 nm technology. With the chosen parameters, a word length of 12 bits and 8 stages in the CORDIC, it is shown that the improved architecture is 20 % smaller and consumes 26 % less power. View full abstract»

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  • Exploring a circuit design approach based on one-hot multi-valued domino logic

    Page(s): 69 - 72
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    In this paper, we report on initial experiments on the feasibility of a circuit design approach that is based on one-hot multi-valued decomposition of a logic netlist. A binary-valued logic netlist would first be decomposed into multi-valued logic nodes (with multi-valued inputs as well as outputs). For an arbitrary multi-valued logic node, this paper presents a circuit and layout design approach. We first synthesize the multi-valued logic node, using multi-valued decision diagrams (MDDs) to represent each output value of the multi-valued logic node. Each such MDD represents a binary valued output function, on one-hot multi-valued inputs. Assuming that the multi-valued logic node has a κ-valued output, then κ such MDDs completely represent the logic of the multi-valued node. Each such MDD is realized using a very regular, compact domino logic based layout structure. We have compared the delay, area, power and power-delay product of our approach with the same logic functionality implemented in standard cells. Averaged over 15 examples, our approach yields a 22% (26%) improvement in delay, 33% (17%) improvement in area, 42% (29%) improvement in power and a 52% (45%) improvement in power-delay product compared to a delay mapped (area mapped) standard cell based realization of the same functionality. View full abstract»

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  • TSPC-DICE: A single phase clock high performance SEU hardened flip-flop

    Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (884 KB) |  | HTML iconHTML  

    This paper presents a true single-phase clock (TSPC) flip-flop that is robust against radiation-induced single event upsets (SEUs) or soft errors. The flip-flop consists of an input stage that uses a single phase clock to pass the data to a storage unit at the positive edge of the clock. The single phase clock enables designing power-efficient and easily-routed clock-tree and reducing the NBTI effect on the setup and hold times. The storage unit consists of the SEU robust dual interlocked cell (DICE), which has four nodes that replicate the data bit and its complement for recovering from a single event transient (SET). Two nodes with the same logic value inside the storage unit drive a C-element at the output. The C-element masks the propagation of any SET from the internal nodes of the storage unit to the output. The proposed flip-flop consists of only 22 transistors, consumes smaller area, and exhibits as much as 12% lower power-delay product when compared with a recently reported SEU robust flip-flop implemented in a commercial 65nm CMOS technology. View full abstract»

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