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Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on

Date 11-13 Aug. 2008

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Displaying Results 1 - 25 of 79
  • Towards a green electronic world: a collaborative approach

    Publication Year: 2008 , Page(s): 1 - 2
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (115 KB)  

    Summary form only given. Increasing power density of complex SoC's have made low-power a topic of interest in the industry. Power considerations in portable and wireless consumer devices have become a key part of many product specifications. Even for wired devices and other industry segments in which battery power has not traditionally been an issue, considerations of packaging, reliability, and cooling costs brings power firmly to the forefront at smaller geometries. In particular, as designs migrate to sub-90 nm process nodes, power management becomes a serious concern across the entire design and manufacturing chain. To help design teams, there is a need to adopt advanced power reduction techniques, where a complete low power solution is needed for the design, verification, and implementation of low-power chips. Since the challenge spans across the design chain, industry collaboration is an imperative. View full abstract»

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  • Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits

    Publication Year: 2008 , Page(s): 3 - 8
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (359 KB) |  | HTML iconHTML  

    This paper presents modeling of manufacturing variability and body bias effect for subthreshold circuits based on measurement of a device array circuit in a 90 nm technology. The device array consists of P/NMOS transistors and ring oscillators. This work verifies the correlation between the variation model extracted from IV measurement results and oscillation frequencies, which means the transistor-level variation model is examined and confirmed in terms of circuit performance. We demonstrate that delay variations of subthreshold circuits are well characterized with two parameters - threshold voltage and subthreshold swing parameter. We reveal that body bias effect is a less statistical phenomenon and threshold voltage shift by body biasing can be modeled deterministically. View full abstract»

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  • Optimal technology selection for minimizing energy and variability in low voltage applications

    Publication Year: 2008 , Page(s): 9 - 14
    Cited by:  Papers (11)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (301 KB) |  | HTML iconHTML  

    Ultra Low voltage operation has recently drawn significant attention due to its large potential energy savings. However, typical design practices used for super-threshold operation are not necessarily compatible with the low voltage regime. Here, radically different guidelines may be needed since existing process technologies have been optimized for super-threshold operation. We therefore study the selection of the optimal technology in ultra low voltage designs to achieve minimum energy and minimum variability which are among foremost concerns. We investigate five industrial technologies, from 250 nm to 65 nm. We demonstrate that mature technologies are often the best choice in very low voltage applications, saving as much as ~1800X in total energy consumption compared to a poorly selected technology. In parallel, the effect of technology choice on variability is investigated, when operating at the energy optimal design point. The results show up to a 4X improvement in delay variation due to global process shift and mismatch when using the most advanced technologies despite their large variability at nominal Vdd. View full abstract»

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  • Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology

    Publication Year: 2008 , Page(s): 15 - 20
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%. View full abstract»

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  • Enhancing beneficial jitter using phase-shifted clock distribution

    Publication Year: 2008 , Page(s): 21 - 26
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1004 KB) |  | HTML iconHTML  

    Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the "beneficial jitter" effect and presents an accurate analytical model which is verified with HSPICE. Based on our model, a phase-shifted clock distribution technique is proposed to enhance the beneficial jitter effect. By having an optimal phase shift between the supply noise and the clock period, the timing margin can be improved by 2.5X to 15% of the clock period. The benefit of the proposed technique is equivalent to that of having a 5X larger decoupling capacitor. View full abstract»

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  • Dynamic virtual ground voltage estimation for power gating

    Publication Year: 2008 , Page(s): 27 - 32
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    With the technology moving into the deep sub-100 nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a promising technique. Our research emphasizes the virtual ground voltage (VVG) as the key to make critical design trade-offs for power gating. We develop an accurate model to estimate the dynamic VVG value of a circuit block as a function of time after its ground is gated. Experimental results show that the model has less than 1% average error compared with HSPICE results. The CAD tool implemented based on the model has a 100 times speedup over HSPICE. View full abstract»

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  • A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops

    Publication Year: 2008 , Page(s): 33 - 38
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (265 KB) |  | HTML iconHTML  

    This paper presents a novel technique to minimize the total power consumption of a synchronous linear pipeline circuit by exploiting extra slacks available in some stages of the pipeline. The key idea is to utilize soft-edge flip-flops to enable time borrowing between stages of a linear pipeline in order to provide the timing-critical stages with more time to complete their computations. Time borrowing, in conjunction with keeping the clock frequency unchanged, gives rise to a positive timing slack in each pipeline stage. The slack is subsequently utilized to minimize the circuit power consumption by reducing the supply voltage level. We formulate and solve the problem of optimally selecting the transparency window of the soft-edge flip-flops and choosing the minimum supply voltage level for the pipeline circuit as a quadratic program, thereby minimizing the power consumption of the linear pipeline circuit under a clock frequency constraint. Experimental results prove the efficacy of the problem formulation and solution technique. View full abstract»

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  • Power-gating-aware high-level synthesis

    Publication Year: 2008 , Page(s): 39 - 44
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (367 KB) |  | HTML iconHTML  

    A problem inherent in designing power-gated circuits is the overhead of the state-retention storage required to preserve the circuit state in standby mode. Reducing the amount of retention storage is known to be the most influential factor in minimizing the loss of the benefit (i.e. power saving) by power-gating. In this paper, we address a new problem of high-level synthesis with the objective of minimizing the size of retention storage to be used in the power-gated circuits. Specifically, we propose a complete design framework, called HLS-pg, that starts from the power-gating-aware scheduling, allocation, and controller synthesis down to the final circuit layout. The key contribution of the work is to solve the power-gating-aware scheduling problem, namely, scheduling operations that minimizes the number of retention registers required at the power-gating control step, while satisfying resource and latency constraints. In experiments on benchmark designs implemented in 65-nm CMOS technology, HLS-pg generates circuits with 27% less leakage current, with 6% less circuit area and wirelength, compared to the power-gated circuits produced by conventional high-level synthesis. View full abstract»

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  • A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing

    Publication Year: 2008 , Page(s): 45 - 50
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (259 KB) |  | HTML iconHTML  

    We propose a parallel and randomized algorithm to solve the problem of discrete dual-Vt assignment combined with continuous gate sizing which is an important low power design technique in high performance domains. This combinatorial optimization problem is particularly difficult to solve on large-sized circuits. We first introduce a hybrid algorithm which combines the existing heuristics and convex formulations for this problem to achieve a better tradeoff between the runtime of the algorithm and the quality of generated solution. We then extend our algorithm to include parallelism and randomization. We introduce a unique utilization of parallelism to better identify the optimization direction. Consequently, we can reduce both the number of iterations in optimization as well as improve the quality of solution. We further use random sampling to avoid being trapped in local minima and to focus the optimization effort on the more "promising" regions of the solution space. Our algorithm improves the average power by 37% compared to an approach which is based on solving a continuous convex program and applying discretization. Power improvement is over 50% for larger benchmarks for an implementation on a grid of 9 computers. View full abstract»

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  • Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction

    Publication Year: 2008 , Page(s): 51 - 56
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion paradigm between cell-level and block-level granularity, in which each layout row defines the unit of gating, and different rows can be clustered and share the same sleep transistor. Previous works, however, assume the availability of a single virtual ground voltage, thus making the decision of whether to gate or not a given cluster a binary choice: a cluster is either gated or not. In this work, we consider a limited set of virtual ground voltages, which allows us to assign to a cluster the virtual ground voltage that offers the best leakage-performance tradeoff for that cluster. We propose two algorithms for solving two power-gating variants: one in which the entire design is gated (given an allowable delay degradation), and another one in which only a subset of the rows is gated (given an allowable delay degradation and sleep transistor area). Our algorithm automatically finds the set of clusters with optimal virtual ground voltages so as to minimize leakage while respecting timing and area constraints. The number of power-gating domains can be user-bounded, in accordance with power grid or library characterization limitations. Results show that multiple virtual ground allow to improve by more than 34% over existing solutions that gate the entire design, and provide sizable savings also for the case of partial power-gating. View full abstract»

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  • A multi-story power delivery technique for 3D integrated circuits

    Publication Year: 2008 , Page(s): 57 - 62
    Cited by:  Papers (21)  |  Patents (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1053 KB) |  | HTML iconHTML  

    Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some interesting facts and design challenges. A multi-story power delivery technique that can reduce the worst case DC noise by 45% and lower the overhead power consumed in the power supply network by 65% is proposed. A test chip layout in an SOI process, showing a 5.3% area overhead, demonstrates the feasibility of the scheme. View full abstract»

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  • Energy harvesting photodiodes with integrated 2D diffractive storage capacitance

    Publication Year: 2008 , Page(s): 63 - 68
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (433 KB) |  | HTML iconHTML  

    Integrating photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, low-cost energy harvesting wireless systems. To further explore the tradeoffs between optical efficiency and capacitive energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in TSMC's 90 nm CMOS technology. Transient effects from interfacing the photodiodes with switching regulators were examined. A quantitative comparison between 90 nm and 0.35 μm CMOS logic processes for energy harvesting capabilities was carried out. Measurements show an increase in power generation for the newer CMOS technology, however at the cost of reduced output voltage. View full abstract»

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  • Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion

    Publication Year: 2008 , Page(s): 69 - 74
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1333 KB) |  | HTML iconHTML  

    A simple yet effective technique that aims at reducing the energy and latency overheads incurred during the wakeup period of MTCMOS circuits is presented in this paper. One or more high-Vth keepers are inserted in MTCMOS combinational logic to reduce the metastability time that causes excessive short circuit current during mode transition and to minimize spurious glitches at internal circuit nodes. Employing the proposed keeper insertion technique in a 16-bit MTCMOS adder, up to 17.5% average wakeup energy and 54.6% wakeup latency reductions are achieved with negligible runtime power and latency overheads, while maintaining the standby energy efficiency of the original MTCMOS design. View full abstract»

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  • Low-power high-accuracy timing systems for efficient duty cycling

    Publication Year: 2008 , Page(s): 75 - 80
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (292 KB) |  | HTML iconHTML  

    Time keeping and synchronization are important services for networked and embedded systems. High quality timing information allows embedded network nodes to provide accurate time-stamping, fast localization, efficient duty cycling schedules, and other basic but essential functions - all of which are required for low power operation. In this paper we present a new type of local clock source called Crystal Compensated Crystal based Timer (XCXT) and a number of novel algorithms that effectively utilize it to achieve low power consumption in wireless sensor networks. The XCXT has timing accuracies similar to timers based on temperature compensated crystal oscillators (TCXO) but has a lower implementation cost and requires less power. Our initial 8MHz prototype unit, using the simplest algorithm, achieves an effective frequency stability of ±1.2ppm and consumes only 1.27mW. On the other hand, commercially available TCXOs with similar stability can cost over 10 times as much and consume over 20mW. In addition to the prototype, we will present algorithms that will improve the XCXT's power consumption by at least 48%, depending on application and environmental conditions. We will also show how XCXT's power efficiency can be improved even further by employing clocks at different frequency when different time granularities are required by an application. View full abstract»

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  • An expected-utility based approach to variation aware VLSI optimization under scarce information

    Publication Year: 2008 , Page(s): 81 - 86
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (383 KB) |  | HTML iconHTML  

    In this research, we propose a novel approach for simultaneous optimization of power, crosstalk noise and delay via gate sizing, in the presence of scarce information about the distribution of the variations. The methodology uses the concepts of utility theory and risk minimization to identify a deterministic equivalent model of the stochastic problem, ensuring high levels of expected utilities of constraints, and significant speedup in the optimization process for large circuits. A comparative study with an existing gate sizing methodology shows that our method is multi-fold faster as well as comparable in terms of the optimization. View full abstract»

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  • SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes

    Publication Year: 2008 , Page(s): 87 - 92
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (500 KB) |  | HTML iconHTML  

    We present a novel power-aware yield enhancement design methodology and reconfiguration scheme for deep submicron SRAM designs. We show that with the continued trend of raising array supply to counter process variations, it is more effective to use a per-element selectable virtual power-supply scenario as opposed to single array supply with traditional redundancy schemes. The element can be a bank, a sub-array, or an independent row/column, and the element's virtual supply value is determined based on fail bitmaps. The technique can also be used in conjunction with traditional redundancy schemes to further improve the efficiency. The supply and redundancy assignments can be obtained by relying on memory reconfiguration algorithms. For this, we propose a greedy yet accurate algorithm that runs in O(nlogn) as opposed to average case O(n2) traditional algorithms. The methodology leads to significant power savings ranging from 20% to 50% for 65 nm technology. We expect the savings to increase in future technologies as leakage powers dominate. To the best of our knowledge, this is the first time such a methodology is applied to SRAM designs. View full abstract»

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  • Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation

    Publication Year: 2008 , Page(s): 93 - 98
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (299 KB) |  | HTML iconHTML  

    Traditionally, spare rows/columns have been used in two ways: either to replace too leaky cells to reduce leakage, or to substitute faulty cells to improve yield. In contrast, we first choose a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for SRAM transistors at design time to reduce leakage, and then substitute the resulting too slow cells by spare rows/columns. We show that due to within-die delay variation of SRAM cells only a few cells violate target timing at higher Vth or Tox; we carefully choose the Vth and Tox values such that the original memory timing-yield remains intact for a negligible extra delay. On a commercial 90 nm process assuming 3% variation in SRAM cell delay, we obtained 47% leakage reduction by adding only 5 redundant columns at negligible area, dynamic power and delay costs. View full abstract»

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  • Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power

    Publication Year: 2008 , Page(s): 99 - 104
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (285 KB) |  | HTML iconHTML  

    The reliability against transient faults poses a significant challenge due to technology scaling trends. Several circuit optimization techniques have been proposed in the literature for preventing soft errors in logic circuits. However, most approaches do not incorporate the effects of other design metrics like delay and power while optimizing the circuit for soft error protection. In this work, we develop a first order model of the soft error phenomenon in logic circuits and incorporate power and delay metrics to formulate a convex programming based reliability-centric gate sizing technique. The proposed algorithm has been implemented and validated on the ISCASS85 benchmarks. Experimental results indicate that our multi-objective optimization technique can achieve significant reductions in soft error rate with simultaneous optimization of delay and power. View full abstract»

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  • Variation-aware gate sizing and clustering for post-silicon optimized circuits

    Publication Year: 2008 , Page(s): 105 - 110
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (289 KB) |  | HTML iconHTML  

    As technology is aggressively scaled, nano-regime VLSI designs are becoming increasingly susceptible to process variations. Unlike pre-silicon optimization, post-silicon techniques can tune the individual die to better meet the power-delay constraints. This paper proposes a variation-aware methodology for the simultaneous gate sizing and clustering for post-silicon tuning with adaptive body biasing. The proposed methodology uses an accurate table look-up model and fully explores the interaction between gate sizing and optimal body bias based clustering. In addition, it is suitable for industrial test cases with tens of thousands gates. Our optimization methodology includes a body bias distribution alignment strategy to mitigate the impact of critical gates. In this way, the cluster's body bias voltage is not simply determined by only a few critical gates. We also prove the linear dependence between the mean of the body bias probability distribution and the gate size. Based on this, we further investigate a simultaneous sizing and re-clustering algorithm for better leakage savings. A circuit re-balancing and gate snapping scheme is then suggested to map the solution to a standard cell library. Compared with arecently-reported method, the proposed methodology can obtain on average 25.5% leakage saving at nearly the same run time. View full abstract»

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  • Error-resilient low-power Viterbi decoders

    Publication Year: 2008 , Page(s): 111 - 116
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (692 KB) |  | HTML iconHTML  

    Two low-power Viterbi decoder (VD) architectures are presented in this paper. In the first, limited decision errors are introduced in the add-compare-select units (ACSUs) of a VD to reduce their critical path delays so that they can be operated at lower supply voltages in absence of timing errors. In the second one, we allow data-dependent timing errors which occur whenever a critical path in the ACSU is excited. Algorithmic noise-tolerance (ANT) is then applied at the level of the ACSU to correct for these errors. Power reduction in this design is achieved by either overscaling the supply voltage (voltage overscaling (VOS)) or designing at the nominal process corner and supply voltage (average-case design). Power savings in the first and second design are 58% and 40% at a coding loss of 0:15 dB and 1:1 dB respectively in a IBM 130 nm CMOS process. View full abstract»

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  • Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators

    Publication Year: 2008 , Page(s): 117 - 122
    Cited by:  Papers (8)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (331 KB) |  | HTML iconHTML  

    In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of minimum operating voltage (VDDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm CMOS ring oscillators (RO's). The measured average VDDmin of inverter RO's increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1 Mega, which indicates the difficulty of the VDD scaling in the large scale subthreshold logic circuits. The dependence of VDDmin on the number of stages is calculated with the subthreshold current model with random threshold voltage (VTH) variations and compared with the measured results, which confirm the tendency of the measurement. View full abstract»

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  • Thermal analysis of 8-T SRAM for nano-scaled technologies

    Publication Year: 2008 , Page(s): 123 - 128
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1405 KB) |  | HTML iconHTML  

    Different sections of a cache memory may experience different temperature profiles depending on their proximity to other active logic units such as the execution unit. In this paper, we perform thermal analysis of cache memories under the influence of hot-spots. In particular, 8-T SRAM bit cell is chosen because of its robust functionality at nano-scaled technologies. Thermal map of entire 8-T SRAM cache is generated using hierarchical compact thermal models while solving the leakage and temperature self consistently. The impact of spatial temperature variations on 8T-SRAM parameters such as local bitline (LBL) sensing delay, noise robustness and bitcell stability are evaluated for 45nm/32nm/22nm bulk CMOS technology nodes. The effectiveness of variable keeper sizing on LBL sensing delay is analyzed. It is predicted that at 22 nm node, the leakage induced temperature rise has severe effects on the 8-T SRAM characteristics. View full abstract»

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  • Analyzing static and dynamic write margin for nanometer SRAMs

    Publication Year: 2008 , Page(s): 129 - 134
    Cited by:  Papers (37)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (468 KB) |  | HTML iconHTML  

    This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on the relationship between static and dynamic write margin metrics. Reliability has become a major concern for SRAM designs in modern technologies. Both local mismatch and scaled VDD degrade read stability and write ability. Several static approaches, including traditional SNM, BL margin, and the N-curve method, can be used to measure static write margin. However, static approaches cannot indicate the impact of dynamic dependencies on cell stability. We propose to analyze dynamic write ability by considering the write operation as a noise event that we analyze using dynamic stability criteria. We also define dynamic write ability as the critical pulse width for a write. By using this dynamic criterion, we evaluate the existing static write margin metrics at normal and scaled supply voltages and assess their limitations. The dynamic write time metric can also be used to improve the accuracy of VCCmin estimation for active VDD scaling designs. View full abstract»

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  • Power management solutions for computer systems and datacenters

    Publication Year: 2008 , Page(s): 135 - 136
    Cited by:  Papers (7)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (124 KB) |  | HTML iconHTML  

    The growing power and cooling requirements of high-density computing systems pose significant challenges for the design and operation of computers and their facilities. The rising operating expenses for datacenters demand the implementation of energy-efficient technologies and the best power management solutions. This tutorial addresses power management and cooling solutions from the individual computer system level to the datacenter. The audience will learn about the fundamental nature of the problems, approaches to developing solutions, available commercial solutions, and current research directions. View full abstract»

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  • Low power design under parameter variations

    Publication Year: 2008 , Page(s): 137 - 138
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (115 KB) |  | HTML iconHTML  

    Design considerations for low-power operations and robustness with respect to variations typically impose contradictory design requirements. Low-power design techniques such as voltage scaling, dual-Vth and gate sizing can have large negative impact on parametric yield under process variations. In this tutorial, we focus on circuit/architectural design techniques for low power under parameter variations. We consider both logic and memory design and encompass modeling, analysis as well as design methodology to simultaneously achieve low power and variation tolerance. Design techniques to minimize power under parametric yield constraint as well as major process adaptation techniques using voltage scaling, adaptive body biasing or logic restructuring will be presented. Techniques to deal with within-die parameter variations in logic and memory circuits primarily caused by random dopant fluctuations will be discussed with emphasis on frequency assignments and body biasing. Finally, we will discuss temperature-aware design, dynamic adaptation to temperature and cover on-going research activities in related area such as low-power and variation tolerant multi-core processor design. View full abstract»

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