By Topic

Green Circuits and Systems (ICGCS), 2010 International Conference on

Date 21-23 June 2010

Filter Results

Displaying Results 1 - 25 of 144
  • Start

    Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (1579 KB)  
    Freely Available from IEEE
  • [Title page]

    Page(s): i - xvii
    Save to Project icon | Request Permissions | PDF file iconPDF (767 KB)  
    Freely Available from IEEE
  • Technical program

    Page(s): 1 - 31
    Save to Project icon | Request Permissions | PDF file iconPDF (2810 KB)  
    Freely Available from IEEE
  • Author index

    Page(s): 1 - 25
    Save to Project icon | Request Permissions | PDF file iconPDF (146 KB)  
    Freely Available from IEEE
  • Green design techniques for RF front-end circuits

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1418 KB) |  | HTML iconHTML  

    In the near decade, following the advances in CMOS technology, RF CMOS circuits have been extensively applied in consumer products and wireless communication systems. Meanwhile, the demand of green design mechanism is becoming more and more important for circuit designs. This paper proposes the green design strategies for RF circuits, such as PA, LNA, mixer, and VCO. The design strategies focus on not only the low power consumption with reused bias current but also the small chip area for low spurious environment contamination. For the low-power design, some published literatures have been adopted the operation voltage from 3V down to only 0.2V, to save the dissipated dc power from tens mW to several hundreds of μW. Additionally, many design strategies and green figures of merit (GFOM) are also presented and proposed in this paper, for the future green RF circuit design. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Green energy harvesting technology in 3D IC

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (419 KB) |  | HTML iconHTML  

    Three dimensional integrated circuit (3D IC) is recognized as the breakthrough technology to be widely used in semiconductor industries in the next three years. The green energy harvesting technology is important for future 3D IC development. In this paper, the material and fabrication of the thermocouple structures are investigated for memory-on-logic 3D IC. The efficiency of such a green energy harvesting system is evaluated. By utilizing the large temperature difference between memory and logic layers, the proposed thermocouple structures convert the wasted heat in the logic layer into electricity in the memory layer and provide the green energy for the memory operations. The significance of this proposed energy harvesting technology is to enable innovations that establish green energy 3D ICs for many future applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A green FFT processor with 2.5-GS/s for IEEE 802.15.3c (WPANs)

    Page(s): 9 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2149 KB) |  | HTML iconHTML  

    This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the 2.59 Gigasample/s throughput requirements, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced and the proposed radix-16 FFT butterfly processing element (PE) can be optimally pipelined. Specifically, the radix-16 butterfly PE consists of one radix-4 and two radix-2 cascaded pipelined butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to the optimized pipelined structure. Hardware reuse and low-power schemes are also devised to reduce both area and power consumption. Moreover, a multibank memory scheme is used to support up to 16-times I/O capability of a single-bank memory, which can greatly reduce the input/output time of FFT data samples. As a result, the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that the proposed design has 2.59 GS/s throughput and it consumes 103.5 mW by using UMC 90nm process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Energy-efficient 128∼2048/1536-point FFT processor with resource block mapping for 3GPP-LTE system

    Page(s): 14 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1492 KB) |  | HTML iconHTML  

    In this paper, we propose an energy-efficient 128~2048/1536-point partial FFT processor for the resource block mapping in the 3GPP-LTE OFDMA system. First, we present a modified partial cached-FFT algorithm with radix-2/22/3 operations for different resource block allocation in the OFDMA system. Then, based on the proposed algorithm, we build up the architecture of radix-2/22/3 cached-FFT processor. This processor can partially compute the selected resource blocks assigned by the base-station with the virtual resource block (VRB) to physical resource block (PRB) mapping in the 3GPP-LTE system. The proposed FFT processor was designed and implemented using TSMC 0.18 μm 1P6M CMOS technology. Measurement results of the test chip show that the FFT processor runs at 35 MHz with 11.29 mW power consumption and it consumes 0.5 to 1.29 nJ per FFT point. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low power biomedical signal processing system-on-chip design for portable brain-heart monitoring systems

    Page(s): 18 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2027 KB) |  | HTML iconHTML  

    In this paper, an overview of a brain-heart monitoring system is first given. The latest development in miniature brain-heart monitoring system for emerging health applications is highlighted. Finally, the development of a low power biomedical signal processing and image reconstruction SoC design is presented. The significance of this SoC is to enable practical developments of portable real-time brain-heart monitoring systems. The proposed architecture comprises a novel functional near-infrared (fNIR) diffuse optical tomography system for brain imaging, an independent component analysis (ICA) processor for electroencephalogram (EEG) signal analysis, and a heart rate variability (HRV) analysis processor for electrocardiogram (ECG) signal analysis. Biomedical signals acquired from front-end sensor modules are processed in real-time or bypassed according to user settings. The processed data or biomedical signals is then losslessly compressed and sent to a remote science station for further analysis and 3D visualization. The final SoC is fabricated in UMC 90nm CMOS technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low power and standard-compliant RDO motion estimation hardware architecture for VBSME

    Page(s): 24 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2264 KB) |  | HTML iconHTML  

    Motion Estimation (ME) is the most computationally intensive part in the whole video compression process. The ME algorithms can be divided into full search ME (FS) and fast ME (FME). The FS is not suitable for high definition (HD) frame size videos because its relevant high computation load and hard to deal with complex motions in limited search range. A lot of FME algorithms have been proposed which can significantly reduce the computation load compared to FS. Though many kinds of hardware implementations of ME have been proposed, almost all of them fail to consider about the motion vector field (MVF) coherence and rate-distortion (RD) cost which have significant impact to the coding efficiency. In this paper, we propose a novel hardware-oriented motion estimation algorithm called RD Optimized single-MVP-biased FS (RDOMFS), and corresponding highly data reusable hardware architecture. Simulation results show that the proposed ME algorithm performs better RD performance than conventional FME algorithm. The design is implemented with TSMC 0.13 um CMOS technology and costs 103 k gates. At a clock frequency of 61 MHz, the architecture achieves real-time 1920 × 1080 RDO-VBSME at 30 fps. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimisation of real functions of complex matrices for the adaptive estimation of complex sources

    Page(s): 30 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (417 KB) |  | HTML iconHTML  

    The second order Taylor series expansion (TSE) of scalar functions of complex matrices is explored in order to provide a new tool for gradient-based optimisation in the complex domain. The expansion is provided both in the augmented real and complex matrix spaces, as well as the multidimensional complex domain. The duality (isomorphism) between the augmented spaces is established and consequently the relation of the first- and second-order terms (gradient and Hessian) of the TSE in these spaces are introduced. Finally, a study of the trade-off between performance and computational complexity of algorithms for the estimation of complex sources in the two augmented spaces is performed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Energy-efficient distributed parameter estimation with partial updates

    Page(s): 36 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB) |  | HTML iconHTML  

    This paper presents an innovative approach to distributed estimation which features partial updates of parameter estimations, thereby offering significant reduction in energy consumption in the sensors. The proposed estimation scheme updates only a subset of the parameters at each iteration. This not only reduces data processing complexity, but also reduces the energy required for diffusing the parameter estimates. In distributed parameter estimation, sensor nodes consume energy not only in processing data, but most costly, in communicating and diffusing updated parameter estimates. Reducing the number of parameters to be updated and diffused are thus an effective way to save in energy consumption. As such, the most fruitful outcome in partial updates is saving in energy required to diffuse those updated parameter estimates. The proposed scheme is a viable alternative to conventional set-membership adaptive algorithms that feature data-dependent selective updates of parameter estimates. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Shrinkage methods applied to adaptive filters

    Page(s): 41 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1297 KB) |  | HTML iconHTML  

    This paper analyzes the use of some regression shrinkage methods in adaptive signal processing. Some shrinkage strategies that render interpretable models can be solved as a linearly-constrained least squares problem and render model coefficients which are exactly zero. As a consequence, they produce estimators which may be more economical and have lower variance than those produced by ordinary least squares estimators, at the price of some bias. Economy, in this case, means less computations, consequently less battery consumption and more sustainable systems. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wind prediction using complex augmented adaptive filters

    Page(s): 46 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB) |  | HTML iconHTML  

    In this paper we discuss a new set of nonlinear adaptive filters based on kernel methods and compare them to the least mean square (LMS) and recursive least squares (RLS) adaptive filters. In recent years a new class of nonlinear kernel adaptive filters have been developed that tradeoff performance for complexity including the Kernel LMS (KLMS) and Kernel RLS (KRLS) algorithms. Earlier work discussed a complex augmented implementation of the kernel algorithms. This paper continues this discussion and compares the performance and complexity of the algorithms for wind time series prediction. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low complexity realization of the sign-LMS algorithm

    Page(s): 51 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    The sign-LMS algorithm is a popular adaptive filter that requires only addition/subtraction but no multiplication in the weight update loop. To reduce the complexity of multiplication that arises in the filtering part of the sign-LMS algorithm, a special radix-4 format is presented in this paper to represent each filter coefficient. The chosen format guarantees sufficient sparsity which in turn reduces the multiplicative complexity as no partial product needs to be computed when the multiplicand is a binary zero. Care, is, however taken to ensure that the weight update process generates the updated weight also in the same chosen radix-4 format, which is ensured by developing an algorithm for adding a 2's complement number with a number given in the adopted radix-4 format. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Area efficient time-shared FIR filters in nanoscale CMOS

    Page(s): 54 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (862 KB) |  | HTML iconHTML  

    Parallelism has been used in the past as a high level architectural transformation for reducing the dynamic power consumption of FIR filters. However increasing the level of parallelism incurs an area penalty. In nanoscale CMOS circuits, leakage power is emerging as the dominant mode of power consumption. Leakage power is strongly correlated to the area and the total number of leaking transistors. This requires the classical area vs. power tradeoffs to be revisited. In addition to reducing the dynamic power, the increased timing slacks in the circuits with a higher degree of parallelism, can also be exploited for implementing the circuit using slower, low-leakage transistors. Hence the efficiency with which an architecture can trade area for increased timing slack is an important consideration for low power design in nanoscale CMOS. The current work shows that the algorithmic strength reduction achieved by fast filter algorithms (FFAs) can be used to design a class of time-shared FIR filters which are more area efficient than traditional structures, under specific conditions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Co-ordinate rotation based low complexity 2D FastICA algorithm and architecture

    Page(s): 60 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    This paper introduces the concept of co-ordinate rotation into the conventional FastICA algorithm and proposes a low complexity 2D FastICA and presents its corresponding architecture. Conventional FastICA uses a preprocessing step involving classical Eigen Value Decomposition problem which, in hardware, is widely solved using Co-ordinate Rotation Digital Computer (CORDIC) technique. The proposed co-ordinate rotation based 2D FastICA algorithm opens up the opportunity to reuse the same CORDIC unit used for the preprocessing step and thus is capable of reducing the hardware complexity of the conventional FastICA algorithm. Along with the formulation and functionality validation of the proposed algorithm, a detailed hardware complexity analysis is also presented in this paper and compared with the already reported architectures. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generalized overlapping digit patterns for multi-dimensional sub-expression sharing

    Page(s): 65 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (645 KB) |  | HTML iconHTML  

    Sub-expression sharing is a technique that can be applied to reduce the complexity of linear time-invariant non-recursive computations by identifying common patterns. It has recently been proposed that it is possible to improve the performance of single and multiple constant multiplication by identifying overlapping digit patterns. In this work we extend the concept of overlapping digit patterns to arbitrary shift dimensions, such as shift in time (FIR filters). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-complexity method for the design of low-delay cosine-modulated filter banks

    Page(s): 69 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (657 KB) |  | HTML iconHTML  

    We present a new method for the design of the cosine-modulated filter bank with low complexity and low delay. The design of such a filter bank is formulated as a nonconvex optimization problem with equality constraints. An iterative scheme is developed to solve this optimization problem. To illustrate the effectiveness of the proposed method, a numerical example is presented. Comparing our method with that in [14], our approach can reduce the number of filter taps by up to 40 % while maintaining a relatively low delay. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A multi-agent differential evolution for linear array synthesis

    Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (717 KB) |  | HTML iconHTML  

    This paper describes a multi-agent differential evolution (MADE) for optimizing linear arrays synthesis. In order to find better solution, each individual of MADE as a agent compete or cooperate with their neighbors, then perform crossover, mutation and selection to diffused global knowledge. And it is used for optimization to reduce the peak side lobe level (PSLL) with minimum element spicing constraints, through dynamic computing lower bound and upper bound, constraints can be handled. Contrast with other result, MADE has greater efficiency and robustness. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A kind of interval combination forecasting method based on induced ordered weighted geometric averaging operators

    Page(s): 77 - 81
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (279 KB) |  | HTML iconHTML  

    With respect to the combination forecasting problem with forecast value and actual value which are interval numbers, this paper introduces IOWGA operators and a new combination forecasting model is proposed to minimize the sum of convex combination with square logarithmic errors of inerval center position and square logarithmic errors of inerval length. The IOWGA weights are calculated by a mathematical programming model. Finally a example is illustrated to show this model improves the combination forecasting accuracy efficiently. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Application of extended Kalman filter in ultra-tight GPS/INS integration based on GPS software receiver

    Page(s): 82 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1061 KB) |  | HTML iconHTML  

    When designing the ultra-tight GPS/INS integration, the architecture of Kalman filter is the key to its successful performance; the crux of this architecture is the measurement model. Aiming at the dependence of numbers of tracked GPS satellites and poor noise immunity in loose and tight integration modes, this paper proposes a new method of ultra-tight integration, using the Q(quadrature) signal from the GPS receiver correlator, receiver position and velocity to form the measurements of the extended Kalman filter. The experiments are carried out based on semi-physics, using the factual data solved by GPS software receiver, and the results show good performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A canonical representation of input-balanced realizations for discrete-time systems

    Page(s): 87 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (783 KB) |  | HTML iconHTML  

    In this paper, based on a matrix factorization a novel structure is proposed for digital system implementation and adaptive filtering applications. The equivalent state-space realization of such a structure is an input-balanced realization. Like the normalized lattice structure, it contains a series of Givens rotations. This proposed structure is simpler than the normalized structure and can be implemented very efficiently using the Coordinate Rotation Digital Computer (CORDIC) techniques. This canonical parametrization is particularly important for ensuring the bounded input bounded output (BIBO) stability when used for adaptive filtering. Numerical examples show that the proposed structure outperforms the traditional direct-form II (DFII) structures as well as the normalized lattice structure in terms of minimizing parameter sensitivity and hence roundoff noise. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An low implementation complexity digital filter without self-sustained oscillations

    Page(s): 93 - 97
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (385 KB) |  | HTML iconHTML  

    In this paper, an efficient sparse structure is derived for digital filters. This structure is actually an improved version of the one reported in but much simpler for implementation. The performance of this structure is analyzed and the corresponding expression of roundoff noise gain is obtained. It is shown that the proposed structure is free of limit cycles. An example is presented to demonstrate the superior performance of the proposed sparse structure to several well-known structures in terms of minimizing the finite word length effects that ultimately can not be avoided in real-time applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Robust ℋ221E; control of networked control systems with access constraints and packet dropouts

    Page(s): 98 - 103
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB) |  | HTML iconHTML  

    We consider a class of networked control systems (NCSs) where the plant has time-varying norm-bounded parameter uncertainties, the network only provides a limited number of simultaneous accesses for the sensors and actuators, and the packet dropouts occur randomly in the network. For this class of NCSs with uncertainties and access constraints as well as packet dropouts, we derive sufficient conditions in the form of linear matrix inequalities that guarantee robust stochastic stabilisation and synthesis of ℋ controller. An example is provided to illustrate our proposed method. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.