13-18 June 2010

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Displaying Results 1 - 25 of 194
  • Awards

    Publication Year: 2010, Page(s):xvi - xxi
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  • Call for contributions [48th Design Automation Conference]

    Publication Year: 2010, Page(s):xxvi - xxix
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  • Executive Committee

    Publication Year: 2010, Page(s):iii - xii
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  • General Chair's message

    Publication Year: 2010, Page(s): i
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  • Proceedings of the 47th design automation conference®

    Publication Year: 2010, Page(s): ii
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  • Reviewers

    Publication Year: 2010, Page(s):xxii - xxv
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  • Thursday keynote address

    Publication Year: 2010, Page(s): xv
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  • Tuesday keynote address

    Publication Year: 2010, Page(s): xiii
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  • Wednesday keynote address

    Publication Year: 2010, Page(s): xiv
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  • Table of contents

    Publication Year: 2010, Page(s):1 - 22
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  • EDA challenges and options: Investing for the future

    Publication Year: 2010, Page(s):1 - 2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (57 KB) | HTML iconHTML

    As the overall economy and semiconductor industry emerges from one of the worst recessions in years, it is time to take stock of EDA challenges and its future. This panel will focus on which challenges will surge and dominate EDA over the course of next several years and which challenges we can sell short. View full abstract»

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  • Quantifying and coping with parametric variations in 3D-stacked microarchitectures

    Publication Year: 2010, Page(s):144 - 149
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (345 KB) | HTML iconHTML

    Variability in device characteristics, i.e., parametric variations, is an important problem for shrinking process technologies. They manifest themselves as variations in performance, power consumption, and reduction in reliability in the manufactured chips as well as low yield levels. Their implications on performance and yield are particularly profound on 3D architectures: a defect on even a sing... View full abstract»

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  • Cost-driven 3D integration with interconnect layers

    Publication Year: 2010, Page(s):150 - 155
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (656 KB) | HTML iconHTML

    The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a promising and scalable solution for interconnecting the cores in CMPs, however it consumes significant portion of the total die area. In this paper, we propose to decouple the interconnect fabric from computing and storage ... View full abstract»

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  • A multilayer nanophotonic interconnection network for on-chip many-core communications

    Publication Year: 2010, Page(s):156 - 161
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (598 KB) | HTML iconHTML

    Multi-core chips or chip multiprocessors (CMPs) are becoming the de facto architecture for scaling up performance and taking advantage of the increasing transistor count on the chip within reasonable power consumption levels. The projected increase in the number of cores in future CMPs is putting stringent demands on the design of the on-chip network (or network-on-chip, NOC). Nanophotonic interco... View full abstract»

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  • Virtual channels vs. multiple physical networks: A comparative analysis

    Publication Year: 2010, Page(s):162 - 165
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (618 KB) | HTML iconHTML

    Packet-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoid deadlock and optimize the bandwidth of the physical channels in exchange for a more complex design of the routers. Another, possibly alternative, approach is to build multiple parallel physical networks (multi-planes) w... View full abstract»

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  • An efficient dynamically reconfigurable on-chip network architecture

    Publication Year: 2010, Page(s):166 - 169
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (291 KB) | HTML iconHTML

    In this paper, we present a reconfigurable architecture for NoCs on which arbitrary application-specific topologies can be implemented. The proposed NoC can dynamically tailor its topology to the traffic pattern of different applications at run-time. The run-time topology construction mechanism involves monitoring the network traffic and changing the inter-node connections in order to reduce the n... View full abstract»

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  • An AIG-based QBF-solver using SAT for preprocessing

    Publication Year: 2010, Page(s):170 - 175
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (583 KB) | HTML iconHTML

    In this paper we present a solver for Quantified Boolean Formulas (QBFs) which is based on And-Inverter Graphs (AIGs). We use a new quantifier elimination method for AIGs, which heuristically combines cofactor-based quantifier elimination with quantification using BDDs and thus benefits from the strengths of both data structures. Moreover, we present a novel SAT-based method for preprocessing QBFs... View full abstract»

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  • Analyzing k-step induction to compute invariants for SAT-based property checking

    Publication Year: 2010, Page(s):176 - 181
    Cited by:  Papers (1)  |  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (411 KB) | HTML iconHTML

    This paper proposes enhancements to SAT-based property checking with the goal to increase the spectrum of applications where a proof of unbounded validity of a safety property can be provided. For this purpose, invariants are computed by reachability analysis on an abstract model. The main idea of the paper consists in a BDD-based analysis of k-step-induction on the abstract model and its use to g... View full abstract»

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  • Coverage in interpolation-based model checking

    Publication Year: 2010, Page(s):182 - 187
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (603 KB) | HTML iconHTML

    Coverage is a means to quantify the quality of a system specification, and is frequently applied to assess progress in system validation. Coverage is a standard measure in testing, but is very difficult to compute in the context of formal verification. We present efficient algorithms for identifying those parts of the system that are covered by a given property. Our algorithm is integrated into st... View full abstract»

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  • An efficient algorithm to verify generalized false paths

    Publication Year: 2010, Page(s):188 - 193
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (243 KB) | HTML iconHTML

    Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem because of the inherent computational cost, and because in practice false paths are not specified one full path at a time. Instead designers use generalized false paths, which represent a set of paths. For instance the SD... View full abstract»

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  • A parallel integer programming approach to global routing

    Publication Year: 2010, Page(s):194 - 199
    Cited by:  Papers (1)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (429 KB) | HTML iconHTML

    We propose a parallel global routing algorithm that concurrently processes routing subproblems corresponding to rectangular subregions covering the chip area. The algorithm uses at it core an existing integer programming (IP) formulation-both for routing each subproblem and for connecting them. Concurrent processing of the routing subproblems is desirable for effective parallelization. However, ac... View full abstract»

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  • Multi-threaded collision-aware global routing with bounded-length maze routing

    Publication Year: 2010, Page(s):200 - 205
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (588 KB) | HTML iconHTML

    Modern global routers use various routing methods to improve routing speed and the quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) to perform much faster routing than traditional maze routing algorithms. The proposed sequential global router, whic... View full abstract»

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  • Two-sided single-detour untangling for bus routing

    Publication Year: 2010, Page(s):206 - 211
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (450 KB) | HTML iconHTML

    In this paper, based on the optimality of hierarchical bubble sorting, the problem of two-sided single-detour untangling for single-layer bus routing is firstly formulated. Compared with an optimal O(n3) algorithm[4] for one-sided single-detour untangling without capacity consideration, an optimal O(n2) algorithm is proposed to solve the two-sided single-detour untangling pro... View full abstract»

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  • An optimal algorithm for finding disjoint rectangles and its application to PCB routing

    Publication Year: 2010, Page(s):212 - 217
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (832 KB) | HTML iconHTML

    The maximum disjoint subset (MDS) of rectangles is a subset of non-overlapping rectangles with the maximum total weight. The problem of finding the MDS of general rectangles has been proven to be NP-complete in [6]. In this paper, we focus on the problem of finding the MDS of boundary rectangles, which is an open problem and is closely related to some difficult problems in PCB routing. We propose ... View full abstract»

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  • Who solves the variability problem?

    Publication Year: 2010, Page(s):218 - 219
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (107 KB) | HTML iconHTML

    Although innovations in manufacturing technology help in reducing variations, IC design variations are a fact of life. In addition to random variations, systematic stress induced variations are becoming increasingly important. This panel will bring the diverse views from academia, foundries, fabless and IDM communities to address various topics on next generation solutions for variability, with th... View full abstract»

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