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Test Symposium (ETS), 2010 15th IEEE European

Date 24-28 May 2010

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  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • [Copyright notice]

    Page(s): 1
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    Freely Available from IEEE
  • Table of contents

    Page(s): 1 - 5
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  • Foreword

    Page(s): 1
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  • Organizing commitee

    Page(s): 2 - 4
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  • ETS 2009 Best Paper

    Page(s): 5
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  • TTTC: Test Technology Technical Council

    Page(s): 6 - 8
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  • Plenary presentations: Keynote: The product complexity and test — How product complexity impacts test industry

    Page(s): 9
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    Summary form only given. One of the driving forces behind the semiconductor industry has been Moore's law. In abstract Moore's law says the number of transistors per square inch on integrated circuits will double every 18 months. Doubling transistor count in rough approximation doubles complexity. To keep the same cost, yield at the new process node must be similar to the previous node. Further, to maintain the cost of test as a percentage of AUC, then test time per transistor or cost of test per second have to be reduced by 50% in the same time lines. The research and development driven in yield management, tester development, test development and DFT have allowed an ongoing cost profile that allows for economic profile required to sustain semiconductor expansion. This talk will explore both historical and real time issues related to complexity and the test industry. View full abstract»

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  • Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance

    Page(s): 10
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    The functions required of real-time systems in the future such as the ability to see or hear, understand and react to external stimulus and the environment in much the same way that humans do, will force underlying communication and computing platforms to operate across very large changes in instantaneous workload. Supporting such workload variations on resource-constrained mobile systems will require new design approaches that cut across the traditional boundaries between the processing, mixed-signal, wireless, and sensor/ actuator (physical) domains, as well as the layers of each domain, i.e. circuit, architecture, algorithm, and application. Due to components fabricated in aggressive nanoscale technologies, such cyber-physical systems must deal with the impact of manufacturing process variations and component failures as well as different environmental conditions (temperature, noise environment) while operating in the most reliable manner with respect to mission goals. An integrated approach to designing such systems that utilizes real-time, cross-domain control and adaptation to operate the system at an “optimal” point that minimizes power consumption while meeting error resilience and performance constraints across different workloads and operating environments is proposed. The core strategy relies on the design and use of tunable algorithms, tunable architectures and tunable circuits that have the capability to trade off power vs. performance. Adaptation is performed by sensing the operating environment and workload using hardware and software “sensors” and dynamically tuning the system via an optimal control law. A critical observation is that this control law depends on the health of the system when power minimization is a key objective. The core ideas are demonstrated using a video surveillance system as a test case. View full abstract»

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  • Adaptive test directions

    Page(s): 12 - 16
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    This paper describes the development of adaptive test in response to the ever growing need to dynamically and cost effectively tailor IC testing to discriminately manage manufacturing process variations. Various degrees of adoption are presented, together with benefits and examples of it's use. Finally, challenges for future development are discussed. View full abstract»

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  • Production test challenges for highly integrated mobile phone SOCs — A case study

    Page(s): 17 - 22
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    Production test is a significant driver of semiconductor manufacturing cost. Test cost is highly influenced by the test concept of a product. This paper gives an overview over the test concept of a complex mobile phone SOC. The particular example is a highly integrated SOC for entry-level mobile phones. The SOC consists, besides digital processing units, of a variety of embedded M/S blocks, an embedded FM radio, and a complete RF transceiver for mobile communication. The paper describes the production test approaches for different groups of embedded circuitry, e.g. digital logic, mixed-signal, etc. Design-for-Test measures are briefly described. A breakdown of relative test times, proportional to production test cost, with respect to different groups of circuitry is presented. Limitations of existing test equipment and future challenges in order to further reduce test cost for complex SOCs are explained based on industrial implementation experience. View full abstract»

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  • Test-architecture optimization for TSV-based 3D stacked ICs

    Page(s): 24 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (662 KB) |  | HTML iconHTML  

    Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D stacked ICs implemented using Through-Silicon Vias (TSVs) technology. We consider 3D-SICs with both fixed given and yet-to-be-designed test architectures on each die and show that both corresponding problem variants are NP-hard. We next present mathematical programming techniques to derive optimal solutions for these problems. Experimental results for three handcrafted 3D-SICs of various SOCs from the ITC'02 SOC test benchmarks show that compared to the baseline method of sequentially testing all dies in a stack, the proposed solutions can achieve up to a 57% reduction in test time. We also show that increasing the number of test pins provides a greater reduction in test time compared to an increase in the number of TSVs. Furthermore, it is shown that 3D stacks with large and complex dies at lower layers require less test time than stacks with complex dies at higher layers. View full abstract»

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  • A low-cost and scalable test architecture for multi-core chips

    Page(s): 30 - 35
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    Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan cells of the cores under test are reused as the pipeline registers of the TAM such that the area cost of the proposed test architecture is low. Experimental results show that the proposed test architecture only consumes about 2.6% area for a multi-core chip with 16 Advanced Encryption Standard (AES) cores. Also, the test time for 16 AES cores is only about 1.004 times of that for a single AES core. View full abstract»

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  • On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking

    Page(s): 36 - 41
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    Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSV) promise high-performance low-power functionality in a smaller form factor at lower cost. Stacking entire wafers has attractive benefits, but unfortunately suffers from low compound stack yield, as one cannot prevent to stack a bad die to a good die or vice versa. Matching individual wafers from repositories of pre-tested wafers to each other is a simple yet effective method to significantly increase the compound stack yield. In this paper, we present a mathematical model, which shows that the yield increase depends on (1) the number of stack tiers, (2) the number of dies per wafer, (3) the die yield, and (4) the repository size. Simulation results demonstrate that, for realistic cases, relative yield increases of 0.5% to 10% can be achieved. We also show that the required investment, in terms of a limited increase in either test or package costs, is typically well justified. View full abstract»

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  • On the use of standard digital ATE for the analysis of RF signals

    Page(s): 43 - 48
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    In this paper, we investigate the use of standard digital ATE for the analysis of FM-modulated RF signals. The key idea is to use the 1-bit digitizer of a digital test channel in order to convert the frequency information contained in a FM-modulated signal into a timing information contained in a digital bit stream; a post-processing algorithm based on the concept of zero-crossing detection is then employed to retrieve this information. Coherent under-sampling is exploited to extend the capabilities of test equipment with a limited sampling frequency for the analysis of high-frequency signals. The proposed approach is evaluated on two different case studies related to LTE and GSM communication standards. Both simulation and hardware experiments are presented to demonstrate the viability of the technique. View full abstract»

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  • Sensors for built-in alternate RF test

    Page(s): 49 - 54
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    The paper discusses a variety of sensors to enable a built-in test in RF devices. The list of sensors includes dummy circuits, process control monitors, DC probes, an envelope detector, and a current sensor. Dummy circuits and process control monitors are simple circuits that do not tap into the signal path of the RF device. Instead, they monitor the device by virtue of being subject to the same process variations. Their outputs form an alternative measurement pattern which can be mapped to the performances of the device using a typical alternate test flow. The rest of the sensors are physically connected to the RF device, thus they can detect random catastrophic defects within it and, as an auxiliary benefit, they can improve the accuracy in predicting its performances. The degradation that these sensors incur is carefully assessed and the RF device is co-designed with them to correct for the losses. The operation and test efficiency of the sensors is demonstrated for the case of an RF LNA using post-layout simulations. View full abstract»

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  • Low-cost signature test of RF blocks based on envelope response analysis

    Page(s): 55 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB) |  | HTML iconHTML  

    This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach. View full abstract»

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  • Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging

    Page(s): 62 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB) |  | HTML iconHTML  

    Scan is a known design-for-test technique in manufacturing test that has been successfully applied also to aid post-silicon debugging on testers. However, to achieve real-time observability in-field, embedded trace buffers are needed. In this paper, we discuss how in the presence of enhanced scan chains, trace buffers can be utilized efficiently for real-time debug data acquisition in-field. View full abstract»

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  • Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis

    Page(s): 69 - 74
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    Increased die-to-die and on-die variations in scaled technologies can lead to parametric failures (Read/Write/Access) in embedded SRAMs. Conventionally, SRAM bit-cell failure analysis is based on the Static Noise Margin (SNM), a metric that leads to conservative estimate of design yield. In this paper we present a method of dynamic noise margin (DNM) estimation based on the modeling technique developed that can efficiently estimate failures in bit-cells under parameter variations. The proposed DNM estimation method is fast, and can accurately estimate the SRAM yield. Monte Carlo simulation results show that the proposed DNM closely matches the results from SPICE analysis. View full abstract»

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  • A low-cost built-in self-test scheme for an array of memories

    Page(s): 75 - 80
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    Modern processor and computation-intensive chips typically use the design style of multi-core chip architecture with identical logic and memory cores. Although memory built-in self-test (BIST) is a mature technique for testing embedded memories, testing multiple small memories using small area cost is still a challenge. This paper proposes a low area-cost BIST scheme for an array of memories and interconnections between memory cores and logic cores. To reduce the area cost without incurring long testing time, the BIST scheme tests multiple identical memories in a pipeline and each memory with a serial test interface. Experimental results show that the proposed BIST scheme has small area cost. For example, the proposed BIST scheme for 16 1024×64-bit RAMs only needs about 0.89% hardware overhead. View full abstract»

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  • A two-layer SPICE model of the ATMEL TSTAC™ eFlash memory technology for defect injection and faulty behavior prediction

    Page(s): 81 - 86
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    Flash memories are based on the floating gate technology allowing the write and erase data electronically. Such a technology can be prone to complex defects leading to faulty behaviors. In this paper, we introduce an electrical model of the ATMEL TSTACTM eFlash memory technology. The model is composed of two layers: a functional layer representing the floating gate and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model has been validated by means of simulations and comparisons with ATMEL silicon data. We apply this model for the analysis of defect-induced failures. As a case study, a resistive defect injection is considered. View full abstract»

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  • A transient error tolerant self-timed asynchronous architecture

    Page(s): 88 - 93
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    High runtime failure rate as a result of reliability detractors is one of the major challenges for scaled-CMOS as well as emerging nanotechnologies. This results in multiple faults during life time operation. In this paper we propose a self-timed asynchronous architecture which can tolerate multiple transient bit-flips. This architecture has self-timed property, making it robust against delay variations caused by increased process variations at nanoscale. The proposed architecture can achieve 100% tolerance of single transient faults as well as more than 93% tolerance of multiple faults for failure rate less than 10-2. View full abstract»

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  • Multiple fault diagnosis in crossbar nano-architectures

    Page(s): 94 - 99
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    Bottom up self-assembly of nano-crossbars from carbon nano-tubes and semiconductor nano-wires has shown the potential to overcome the limitations of lithographic fabrication of CMOS for further down-scaling. However, very high permanent and transient fault rates necessitates the incorporation of efficient fault tolerance techniques, capable of handling multiple faults. Self repair provides fault tolerance through fault detection, diagnosis and reconfiguration to recover from permanent faults. In this paper, we present a multiple faults diagnosis scheme based on dual rail error checking frameworks for nano-crossbar architectures. The proposed scheme is capable of identifying multiple faulty crosspoints with very low performance and area overheads. The experimental results show that all of the multiple faults are correctly diagnosed. View full abstract»

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  • Full-circuit SPICE simulation based validation of dynamic delay estimation

    Page(s): 101 - 106
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    Power supply noise may have big impacts on the design performance in the latest technologies. Accurately mapping the IR-drop effect to real delay is a challenging task, which will directly impact the accuracy of IR-drop related performance evaluation, test, and diagnosis. In this paper, we first present our previous work on setting up an IR2Delay database for addressing this issue. We then propose a flow to validate this database by comparing it with full-circuit SPICE simulation results. In this flow, mixed-signal simulation is used, which can reuse the existing digital testbench as stimuli while maintaining the accuracy of SPICE simulation. View full abstract»

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  • On estimation of NBTI-Induced delay degradation

    Page(s): 107 - 111
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    NBTI, which is one of well-known aging phenomena, brings delay degradation in deep submicron VLSIs. In order to detect NBTI-induced delay faults, we need to estimate delay degradation and apply delay test for the circuit in the field. This paper discusses on estimation of NBTI-Induced delay degradation. We first analyze the effect of the delay degradation, and then give a procedure of path selection in which long paths after the delay degradation are selected for the delay test in the filed. Experimental results show that estimation of delay degradation significantly affects path selection, and accurate estimation is important for the test. View full abstract»

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