Date 2-4 June 2010
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Displaying Results 1 - 25 of 61
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[Front cover]
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PDF (108 KB)
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Content
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PDF (209 KB)
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Table of content
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PDF (49 KB)
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High-speed links for memory interface
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PDF (176 KB)
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ESD protection for wideband RF CMOS LNAs
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PDF (433 KB)
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Comparison between isolated SCR & embedded dual isolated SCR power devices for ESD power clamp in C45nm CMOS technology
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PDF (892 KB)
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New transient detection circuit for electrical fast transient (EFT) protection design in display panels
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PDF (1343 KB)
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Fully depleted Silicon-On-Insulator with back bias and strain for low power and high performance applications
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PDF (753 KB)
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Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)
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PDF (598 KB)
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A GPU/CUDA implementation of the collection-diffusion model to compute SER of large area and complex circuits
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PDF (266 KB)
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The power7TM processor SoC
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PDF (320 KB)
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A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder
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PDF (365 KB)
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Pre-existing and process induced defects in high-k gate dielectrics ∼direct observation with EBIC and impact on 1/f noise∼
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PDF (502 KB)
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Modeling the effects of plasma-induced physical damage on subthreshold leakage current in scaled MOSFETs
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PDF (598 KB)
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Design solutions for preventing process induced ESD damage during manufacturing of interconnects
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PDF (718 KB)
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