# IEEE Transactions on Components, Packaging and Manufacturing Technology

## Issue 10 • Oct. 2017

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## Filter Results

Displaying Results 1 - 25 of 26
• ### Front Cover

Publication Year: 2017, Page(s): C1
| PDF (417 KB)
• ### IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

Publication Year: 2017, Page(s): C2
| PDF (135 KB)

Publication Year: 2017, Page(s):1581 - 1582
| PDF (411 KB)
• ### The Effect of Anisotropic Conductive Films Adhesion on the Bending Reliability of Chip-in-Flex Packages for Wearable Electronics Applications

Publication Year: 2017, Page(s):1583 - 1591
| | PDF (2523 KB) | HTML

In this paper, the effects of adhesion properties of anisotropic conductive films (ACFs) interconnection on the chip-in-flex (CIF) bending reliability were investigated. Oxygen plasma treatment was conducted to increase the adhesion strength between ACFs and Si chip or ACFs and flexible printed circuit (FPC) substrates. In order to characterize the enhanced adhesion properties of the CIF packages,... View full abstract»

• ### Under-Bump Metallization Contact Resistance ( $R_{c}$ ) Characterization at 10- $mu text{m}$ Polymer Passivation Opening

Publication Year: 2017, Page(s):1592 - 1597
| | PDF (1868 KB) | HTML

Under-bump metallization Rc is a critical metric for high-density interconnect in electronic devices. We developed a test vehicle to characterize the impact of unit processes on Rc for 10-μm polymer passivation opening. We demonstrate that advanced preclean is necessary to achieve low (Rc <; 20 mQ) for future node extendibility, owing to reduction of both... View full abstract»

• ### Reliability of AuGe Die Attach on DBC Substrates With Different Ni Surface Finishes

Publication Year: 2017, Page(s):1598 - 1607
| | PDF (5352 KB) | HTML

Plated Ni is a commonly used barrier layer for direct bond copper (DBC) substrates used in high-temperature and high-power applications. The Ni plating method can be electrolytic or electroless, and the composition may be pure Ni, Ni:P, or Ni:B. With a melting point of 356 °C, eutectic Au88Ge12 (wt.%) solder preforms can be used for die attach in high-temperature applications up to 325 �... View full abstract»

• ### Effects of Die-Attach Voids on the Thermal Impedance of Power Electronic Packages

Publication Year: 2017, Page(s):1608 - 1616
| | PDF (4616 KB) | HTML

Thermal runaway is among the major failure mechanisms of power semiconductor packages. Thermal dissipation of power electronics depends on the quality of the solder die-attach, any defects such as voids, and delamination-impede heat dissipation that results in hot spots that can cause thermal runaway and/or a premature device failure. Therefore, investigation of thermal impact due to die-attach de... View full abstract»

• ### Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA

Publication Year: 2017, Page(s):1617 - 1624
| | PDF (3874 KB) | HTML

Microfluidic cooling has been demonstrated as an effective means of cooling microelectronic circuits with a very low convective thermal resistance and potential for integration in close proximity to the area of heat generation. However, microfluidic cooling experiments to date have been limited to silicon with resistive heaters representing the heat generating circuitry. In this paper, a micropin-... View full abstract»

• ### Experimental Analysis and FEM Simulation of Antigravity Loop-Shaped Heat Pipe for Radio Remote Unit

Publication Year: 2017, Page(s):1625 - 1633
| | PDF (1753 KB) | HTML

This paper presents the thermal performance analysis of the antigravity loop-shaped heat pipe (AGLSHP) used for radio remote unit. The experiments are conducted by mounting the system vertically over a heat source set above the condenser with forced convection. The transit temperature distributions of the AGLSHP with two different antigravity lengths are measured and evaluated via increasing the i... View full abstract»

• ### BGA Interconnection Reliability in Mirrored Module Configurations

Publication Year: 2017, Page(s):1634 - 1643
| | PDF (2299 KB) | HTML

Interconnection dimensions are becoming more important due to electrical signal timing requirements and stray effects, such as unwanted inductance, leading to increasingly denser packaging. One way to shorten the signal path is to use mirrored structures, where the components are placed on opposite sides of the printed circuit board (PCB). This paper presents thermal cycling test (TCT) results in ... View full abstract»

• ### The Impact of an Incomplete Overlap of a Copper Conductor and the Corresponding Terminal on the Contact Temperature

Publication Year: 2017, Page(s):1644 - 1654
| | PDF (3256 KB) | HTML

By using a specially designed apparatus, the impact of poor contacts caused by an incomplete overlap of a copper conductor and the corresponding terminal of the low-voltage electrical equipment on the contact temperature was tested. The poor contact was simulated using the electrodes of different cross-sectional areas, exposed to different loads. The most frequently used combinations of the contac... View full abstract»

• ### Packaging of High-Gain Multichip Module in Multilayer LCP Substrates at $W$ -Band

Publication Year: 2017, Page(s):1655 - 1662
| | PDF (2686 KB) | HTML

In this paper, we packaged a multichip module (MCM) in multilayer liquid crystal polymer (LCP) substrate using V-shaped wire bond and 3-D-printed housing. In the proposed module, two low-noise amplifiers (LNAs) are cascaded in series to obtain high gain and low noise figure, and multilayer circuit is designed to achieve high assembly density. To minimize mode mismatch between microstrip lines on L... View full abstract»

• ### Design and Fabrication of a Planar Helix Slow-Wave Structure for $C/X$ -Band TWT

Publication Year: 2017, Page(s):1663 - 1669
| | PDF (1763 KB) | HTML

This paper presents the design and fabrication of a planar helix slow-wave structure (SWS) with straight-edge connections at C/X-band frequencies. Besides RF performance, various issues such as vacuum compatibility of materials as well as ease and accuracy of assembly techniques are specially emphasized. The basic SWS is fabricated on a pair of alumina substrates using printed-circuit techniques a... View full abstract»

• ### A Compact Trans-Directional Coupler With Wide Frequency Tuning Range and Superior Performance

Publication Year: 2017, Page(s):1670 - 1677
| | PDF (2154 KB) | HTML

In this paper, a compact coupled-line trans-directional (TRD) coupler with wide continuous frequency tuning range and superior performance is presented. The proposed tunable TRD coupler is composed of three coupled lines, two shunt stubs, and three types of varactors. By providing suitable reverse bias voltages on these varactors, the operating frequency of the proposed TRD coupler can flexibly be... View full abstract»

• ### Novel Reconfigurable 3-D Frequency Selective Surface

Publication Year: 2017, Page(s):1678 - 1682
| | PDF (1682 KB) | HTML

A novel reconfigurable 3-D frequency selective surface (FSS) exhibiting bandstop response is proposed in this paper. The unit cell of the proposed 3-D FSS is constructed from concentric threaded cylinders. The proposed novel 3-D FSS achieves reconfigurability by sliding technique. It offers frequency tuning from 1.86 to 3.10 GHz by sliding the outer cylinder over the inner cylinder. The proposed F... View full abstract»

• ### A Millimeter-Wave Micromachined Air-Filled Slot Antenna Fed by Patch

Publication Year: 2017, Page(s):1683 - 1690
| | PDF (2018 KB) | HTML

In this paper, a millimeter-wave air-filled slot antenna is presented based on bulk silicon microelectromechanical systems micromachining technology. The antenna is suitable for system-in-package application by utilizing this silicon micromachining technique. To achieve high radiation efficiency in millimeter-wave band, three gold-plated silicon layers are bonded together to realize an air-filled ... View full abstract»

• ### Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)

Publication Year: 2017, Page(s):1691 - 1701
| | PDF (2767 KB) | HTML

An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed... View full abstract»

• ### A Wideband Model for On-Chip Interconnects With Different Shielding Structures

Publication Year: 2017, Page(s):1702 - 1712
| | PDF (2859 KB) | HTML

In this paper, a wideband model for on-chip interconnects with different shielding structures is proposed. In order to improve the performance of interconnects, solid ground, floating shields, and parallel ground shields are often employed in real applications. Based on the transmission line theory and electromagnetic wave theory, these three different shielding structures are analyzed and discuss... View full abstract»

• ### Room Temperature Temporary Bonding of Glass Substrates Based on SAB Method Using Si Intermediate Layer

Publication Year: 2017, Page(s):1713 - 1720
| | PDF (2221 KB) | HTML

This paper reports a new technology for bonding and debonding of glass substrates to handle ultrathin glass substrates in the fabrication process of display devices. Based on the surface activated bonding method, the glass substrates were bonded using deposited Si intermediate layers with less than 10 nm thickness by Ar ion beam sputtering. The bond between the glass substrates can endure the high... View full abstract»

• ### Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan-Out Package

Publication Year: 2017, Page(s):1721 - 1728
| | PDF (1698 KB) | HTML

Nowadays, fan-out package is regarded as one of the latest and most potential technologies because it possesses lower cost, thinner profile, and better electrical performance and thermal performance. However, thermally induced warpage in the molding process is a critical issue due to the larger wafer or panel size, the shrinkage of epoxy mold compound (EMC) during the curing stage, and the mismatc... View full abstract»

• ### Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

Publication Year: 2017, Page(s):1729 - 1738
| | PDF (3972 KB) | HTML

In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, reconstituted carrier material and thickness, and die-attach film, on the warpage after postmold... View full abstract»

• ### Characterization of Delamination in Fiber-Reinforced Epoxy-Based PCB Laminates, Using an EBG-Enhanced Planar Microwave Sensor

Publication Year: 2017, Page(s):1739 - 1746
| | PDF (1450 KB) | HTML

A strategy to detect the extent of delamination in fiber-reinforced epoxy-based thermoset polymer used in printed circuit board (PCB) laminates by a planar microwave microstrip sensor has been proposed in this paper. The sensitivity of the sensor probe is improved using electromagnetic band gap (EBG) structures surrounding the planar sensor. The proposed EBG cells acts as a bandstop filter and sup... View full abstract»

• ### Introducing IEEE Collabratec

Publication Year: 2017, Page(s): 1747
| PDF (2265 KB)
• ### IEEE Open Access Publishing

Publication Year: 2017, Page(s): 1748
| PDF (1491 KB)
• ### IEEE Components, Packaging, and Manufacturing Technology Society information for authors

Publication Year: 2017, Page(s): C3
| PDF (56 KB)

## Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

Full Aims & Scope

Managing Editor
Ravi Mahajan
Intel