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Electron Device Letters, IEEE

Issue 12 • Date Dec. 2014

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Displaying Results 1 - 25 of 65
  • Table of contents

    Page(s): C1 - 1142
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  • IEEE Electron Device Letters publication information

    Page(s): C2
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  • Editorial Kudos to Our Reviewers

    Page(s): 1143
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  • Golden List of Reviewers for 2014

    Page(s): 1144 - 1166
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  • Defect-Centric Distribution of Channel Hot Carrier Degradation in Nano-MOSFETs

    Page(s): 1167 - 1169
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    The defect-centric distribution is used, for the first time, to study the channel hot carrier (CHC) degradation. This distribution has been recently proposed for bias temperature instability (BTI) shift and we show that it also successfully describes the CHC behavior. This distribution has the advantage of being described by two physics-based parameters, the average threshold voltage shift produced by a single charge $eta $ and the number of stress-induced charged traps N $_{boldsymbol{t}}$ . We study the behavior of $eta $ and N $_{boldsymbol {t}}$ on nFETs with different geometries for different CHC stress times. As in the case of BTI, we observe that: 1) during the CHC stress, $eta $ is constant and N $_{boldsymbol{t}}$ increases at the same rate of $Delta $ V $_{mathbf {th}}$ and 2) $eta $ scales as 1/Area. We show that the density of charged traps induced by CHC stress strongly increases with reducing channel length, in contrast to BTI, where the density of charged traps is independent of the device geometry. The defect analysis enabled by the defect-centric statistics can be used to deepen our understanding of CHC degradation in nanoscale MOSFETs, where the defects are reduced to a- numerable level. View full abstract»

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  • In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor

    Page(s): 1170 - 1172
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    The source-pocket (p-n-p-n) tunnel field effect transistor (TFET) has a narrow and highly doped N+ pocket layer between the source and channel to enhance the overall performance of the conventional p-i-n TFET. However, realizing this, N+ pocket increases the fabrication complexity since either an epitaxial growth in vertical TFETs or an implantation in planar TFETs is required to create the N+ pocket. In this letter, using the charge plasma concept, we propose a technique to realize an in-built N+ pocket without the need for a separate implantation. We demonstrate using 2-D simulations that the proposed in-built N+ pocket p-n-p-n TFET exhibits a higher $mathrm{I}_{mathrm {mathbf {ON}}}$ ( $sim 20$ times) and a steeper subthreshold swing (25 mV/decade) as compared with the conventional p-i-n TFET. Our approach overcomes the difficulty of creating a narrow N+ pocket doping and thus makes the p-n-p-n TFET more attractive in carrying on with the scaling trend. View full abstract»

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  • Thermionic-Field Emission Barrier Between Nanocrystalline Diamond and Epitaxial 4H-SiC

    Page(s): 1173 - 1175
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    A novel Schottky-like rectifying heterojunction between two low-doped widebandgap semiconductors is presented. The conduction mechanism of p-type nanocrystalline diamond and n-type 4H-SiC with a near-unity ideality factor was determined via two-terminal current-voltage measurements as a function of temperature and SiC doping concentration. $I$ $V$ characteristics at 300 and 510 K were fit at low forward bias with good agreement using thermionic emission theory. A wide temperature range ideality factor analysis revealed a thermionic-field rectifying barrier to low-doped and moderately doped SiC epilayers, which could lead to improved contacts for SiC-based piezoresistors, resonators, and microelectromechanical systems. View full abstract»

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  • Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation

    Page(s): 1176 - 1178
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    We propose another process for fabricating 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) with high channel mobility. The B atoms were introduced into a SiO2/4H-SiC interface by thermal annealing with a BN planar diffusion source. The interface state density near the conduction band edge of 4H-SiC was effectively reduced by the B diffusion and the fabricated 4H-SiC MOSFETs showed a peak field-effect mobility of 102 $mathrm{cm}^{mathrm {mathbf {2}}}$ /Vs. The obtained high channel mobility cannot be explained by counter doping because B atoms act as acceptors in 4H-SiC. We suggest that the interfacial structural change of SiO2 may be responsible for the reduced trap density and enhanced channel mobility. View full abstract»

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  • Superior Reliability of Junctionless pFinFETs by Reduced Oxide Electric Field

    Page(s): 1179 - 1181
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    Superior reliability of junctionless (JL) compared with inversion-mode field-effect transistors (FETs) is experimentally demonstrated on bulk FinFET wafers. The reduced negative bias temperature instability (NBTI) of JL pFETs outperforms the previously reported best NBTI reliability data obtained with Si channel devices and guarantees 10-year lifetime at typical operating voltages and high temperature. This behavior is understood through the reduced oxide electric field and lessened interaction between charge carriers and oxide traps during device operation. These findings encourage the investigation of JL devices with alternative channels as a promising alternative for 7-nm technology nodes meeting reliability targets. View full abstract»

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  • Origin of Device Performance Enhancement of Junctionless Accumulation-Mode (JAM) Bulk FinFETs With High- $kappa $ Gate Spacers

    Page(s): 1182 - 1184
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    In this letter, we investigated the junctionless accumulation-mode (JAM) bulk FinFETs with high- $kappa $ gate spacers showing enhanced device performance in SS, DIBL, and ON/OFF current ratio. We found that origin of the ON-state current enhancement was reduction of the initial energy barrier between the source and channel, and reason for the OFF-state current reduction was ${L} _{mathbf {G}}$ extension caused by the fringing field through high- $kappa $ gate spacers. The off-state leakage current decreased by over one order of magnitude. The ON-state current was remarkably enhanced by 180% over that of low- $kappa $ gate spacers. The high- $kappa $ gate spacer is indispensable for enhancing the performance of the JAM field-effect transistor in a sub 20-nm -gate length regime. View full abstract»

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  • The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances

    Page(s): 1185 - 1187
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    We investigate the impact of metal-interfacial layer-semiconductor source/drain (M-I-S S/D) structure with heavily doped n-type interfacial layer (n+-IL) or with undoped IL on sub-10-nm n-type germanium (Ge) FinFET device performance using 3-D TCAD simulations. Compared to the metal-semiconductor S/D structure, the M-I-S S/D structures provide much lower contact resistivity. Especially, the M-I-S S/D structure with n+-IL provides much lower contact resistivity, resulting in $sim 5 times $ lower contact resistivity than $1times 10^{mathrm {mathbf {-8 }}}~Omega $ - $mathrm{cm}^{mathrm {mathbf {2}}}$ , specified in International Technology Roadmap for Semiconductors. In addition, we found that the M-I-S structure with n+-IL remarkably suppresses the sensitivity of contact resistivity to S/D doping concentration. View full abstract»

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  • Ohmic Contact to n-Type Ge With Compositional W Nitride

    Page(s): 1188 - 1190
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    By varying composition of the $mathrm{WN}_{rm x}$ film electrode, modulation of the Schottky barrier height (SBH) of $mathrm{WN}_{rm x}$ /n-Ge contacts was demonstrated. The effective SBH decreased from 0.52 eV for W/n-Ge contact to 0.47, 0.42, and 0.39 eV for $mathrm{WN}_{rm x}$ /n-Ge contacts with various nitrogen $x$ components, which were 0.06, 0.09, and 0.15, respectively. Ohmic contact property was achieved when the nitrogen component in $mathrm{WN}_{rm x}$ reached $x = 0.19$ . As an explanation, an electrical potential caused by the N-Ge dipoles layer across the $mathrm{WN}_{rm x}$ /n-Ge contact interface is proposed to alleviate the Fermi-level pinning effect. View full abstract»

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  • Highly Strained Si pFinFET on SiC With Good Control of Sub-Fin Leakage and Self-Heating

    Page(s): 1191 - 1193
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    Investigating of ON-current boosting, short channel effect (SCE), and self-heating effect in Si pFinFET on a SiC stress relaxed buffer (SRB) layer is presented compared with SiGe pFinFET on a SiGe-SRB. Both SiC-SRB-based device and SiGe-SRB-based device show mobility boosting due to high compressive channel stress as well as enhanced SCE due to significant suppressing of subfin leakage. However, if self-heating is considered, SiGe-based devices exhibit non-negligible current degradation compared to SiC-SRB-based devices. Even though SiGe channel devices on a SiGe-SRB show better performance compared with SiC-SRB-based device, it is shown that the impact of BEOL reliability should be considered carefully. View full abstract»

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  • Proton Radiation-Induced Void Formation in Ni/Au-Gated AlGaN/GaN HEMTs

    Page(s): 1194 - 1196
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    AlGaN/GaN high-electron mobility transistors (HEMTs) were exposed to 2-MeV protons irradiation, at room temperature, up to a fluence of $6 times 10^{mathrm {mathbf {14}}}$ H+/ $mathrm{cm}^{mathrm {mathbf {2}}}$ . Aside from degradation resulting from radiation-induced charge trapping, transmission electron microscopy and electrical measurements reveal a radiation-induced defect located at the edges of the Ni/Au Schottky gate in the proton-irradiated devices. At the edges of the Ni/Au gate, the Ni of the Ni/Au gate diffused up into the Au layer and migrated into the AlGaN barrier, leaving voids in the Ni layer at the gate edges after irradiation. These radiation-induced voids are caused by diffusion of Ni through vacancy exchange, known as the Kirkendall effect, resulting in reduced gate area and degrading the HEMT performance. View full abstract»

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  • Demonstration of Normally-Off Recess-Gated AlGaN/GaN MOSFET Using GaN Cap Layer as Recess Mask

    Page(s): 1197 - 1199
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    Based on our proposed self-terminating gate recess etching technique, normally-off recess-gated AlGaN/GaN MOSFET has been demonstrated with a novel method using GaN cap layer (CL) as recess mask, which, as a result, simplifies the device fabrication process and lowers the fabrication cost. The GaN CL is capable of acting as an effective recess mask for the gate recess process, which includes a thermal oxidation for 45 min at 650 °C followed by 4-min etching in potassium hydroxide (KOH) at 70 °C. After gate recess process, no obvious change is observed in terms of the surface morphology of the GaN CL, the contact resistance of the Ohmic contact formed directly on the GaN CL as well as the sheet resistance of the two-dimensional electron gas (2-DEG) channel layer under the GaN CL. The fabricated device exhibits a threshold voltage ( (V_{mathrm {th}})) as high as 5 V, a maximum drain current ( (I_{mathrm {rm dmax}})) of (sim 200) mA/mm, a high on/off current ratio of (sim 10^{10}) together with a low forward gate leakage current of (sim 10^{mathrm {-5}}) mA/mm. Meanwhile, the OFF-state breakdown voltage ( (V_{mathrm {br}})) of the device with gate-drain distance of 6 (mu ) m is 450 V. View full abstract»

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  • Enhancement Mode (E-Mode) AlGaN/GaN MOSFET With $10^{-13}$ A/mm Leakage Current and $10^{12}$ ON/OFF Current Ratio

    Page(s): 1200 - 1202
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    Postgate annealing (PGA) in N2/O2 atmosphere at 300 °C for various annealing time is performed on enhancement mode AlGaN/GaN MOSFET fabricated using a self-terminating gate recess etching technique. After 45-min annealing, the device OFF-state leakage current decreases by more than two orders of magnitude and thus a low OFF-state leakage current of $sim 10^{-13}$ A/mm is obtained at room temperature, resulting in an excellent ON/OFF current ratio of $sim 10^{12}$ . At 250 °C, the device still exhibits a low OFF-state leakage current of $sim 10^{-9}$ A/mm and high ON/OFF current ratio of $sim 10^{8}$ . Meanwhile, a strong correlation between the OFF-state leakage current and mesa isolation current is observed as we change the annealing time: 1) the lower the mesa isolation current and 2) the lower the OFF-state leakage current and thus the higher the ON/OFF current ratio. It is the suppression of the mesa isolation current owing to the passivation of atomic layer deposition Al2O3 that leads to the improvement of the OFF-state leakage current and ON/OFF current ratio after PGA. Besides, the device shows no obvious change in terms of its threshold voltage and maximum drain current after PGA. View full abstract»

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  • Off-State Leakage Induced by Band-to-Band Tunneling and Floating-Body Bipolar Effect in InGaAs Quantum-Well MOSFETs

    Page(s): 1203 - 1205
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    The physics of off-state drain leakage ( $I_{off}$ ) in scaled self-aligned InGaAs quantum-well (QW) MOSFETs is investigated through experiments and simulations. Excess $I_{off}$ is observed in InGaAs QW-MOSFETs with very short contact-to-channel spacing. This current bears the marks of band-to-band tunneling (BTBT) that takes place at the drain edge of the channel. However, a pure BTBT current does not explain the observed magnitude of $I_{off}$ nor its gate length dependence. For this, we invoke floating-body bipolar amplification of the BTBT current in the QW channel. Device simulations that include BTBT and drift diffusion are consistent with the magnitude of the experimental $I_{off}$ and its gate length scaling behavior. The understanding derived here suggests a number of paths to mitigate BTBT-induced off-state current in scaled InGaAs QW-MOSFETs. View full abstract»

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  • Silicon Carbide Integrated Circuits With Stable Operation Over a Wide Temperature Range

    Page(s): 1206 - 1208
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    In this letter, silicon carbide MOSFET-based integrated circuits have been designed, fabricated, and successfully tested from −193 °C (80 K) to 500 °C. Silicon carbide single MOSFETs remained fully operational over a 700-°C wide temperature range and exhibited stable $I$ $V$ characteristics. The circuits that include operational amplifier (op-amp), 27-stage ring oscillator, and buffer were tested and shown to be functional up to 500 °C with relatively small performance variation between 300 °C and 500 °C. High-temperature evaluation of these circuits confirmed stable operation and survivability of both the ring oscillator and op-amp for more than 100 h at 500 °C. View full abstract»

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  • Composition- and Doping-Graded-Base InP/InGaAsSb Double Heterojunction Bipolar Transistors Exhibiting Simultaneous (f_{t}) and (f_{textrm {max}}) of Over 500 GHz

    Page(s): 1209 - 1211
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    We demonstrate composition- and doping-graded-base InP/InGaAsSb double heterojunction bipolar transistors (DHBTs) with a passivation ledge fabricated in a self-aligned process with i-line lithography. We obtained a high current gain of 52 and high breakdown voltage of 5 V for 0.2- (mu ) m-emitter DHBTs featuring 30-nm-thick composition- and doping-graded InGaAsSb base and 100-nm-thick InP collector. The HBTs exhibit an ({f} _{t}) of 501 GHz and an ({f} _{textrm {max}}) of 503 GHz at a collector current density of 10.6 mA/ (mu ) m (^{2}) . View full abstract»

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  • Design and Simulation of Two-Dimensional Superlattice Steep Transistors

    Page(s): 1212 - 1214
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    We report design of double-gate metal–oxide–semiconductor field-effect-transistors having InGaAs/InAlAs superlattices between the N+ source and a planar InGaAs channel. As with nanowire superlattice transistors, the 2-D superlattice bandgap reduces injection into the channel of electrons having energy above the source Fermi energy. Simulated ballistic transport characteristics of FETs using a three-well superlattice show 29–37.5-mV/decade minimum subthreshold swing and 390-A/m ON-current given 0.1-A/m OFF-current and a 0.2 V power supply. View full abstract»

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  • 650-GHz Resonant-Tunneling-Diode VCO With Wide Tuning Range Using Varactor Diode

    Page(s): 1215 - 1217
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    We fabricated a wide-range varactor-tuned terahertz oscillator using a resonant tunneling diode (RTD). An AlAs/InGaAs double-barrier RTD and a varactor-diode mesa were integrated into a 20- $mu $ m-long slot antenna. A wide tuning range of $sim 11$ % (70 GHz) of the center frequency of 655 GHz was achieved by changing the depletion-layer capacitance of the varactor diode with a dc sweep from −4 to 0.5 V. The dependence of the output power on the varactor-diode bias was also measured. These experimental results agreed well with theory. View full abstract»

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  • GaAsSb-Based DHBTs With a Reduced Base Access Distance and (f_{mathrm {T}}/f_{mathrm {MAX}}=) 503/780 GHz

    Page(s): 1218 - 1220
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    We report InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with simultaneous current and power gain cutoff frequencies of ({f} _{mathbf {T}}/f_{mathrm {mathbf {MAX}}}=) 503/780 GHz. Devices with a 0.2 (times ) 4.4 (mu ) m (^{mathrm {mathbf {2}}}) emitter area feature a peak DC current gain (beta ) = 17 and a common-emitter breakdown voltage BV (_{mathrm {mathbf {CEO}}}) = 4.1 V. To the best of our knowledge, the present transistors are the first GaAsSb-based DHBTs to feature ({f} _{mathrm {mathbf {MAX}}}) > 750 GHz. The progress in RF performance is enabled by a reduction of the base access resistance and base-collector capacitance achieved via an improved self-aligned emitter etching procedure. View full abstract»

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  • GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths

    Page(s): 1221 - 1223
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    In this letter, a sub-10-nm n-type GaSb–InAs heterojuction tunnel field-effect transistor (Het-j TFET), having n+-doped underlap layer of InAs between source and channel is proposed, which exhibits low subthreshold swing (SS) over a large range of currents. The proposed device is compared with conventional p-i-n GaSb-InAs Het-j TFET having the same physical gate length of 9 nm. Using ballistic tight binding-based Non-Equilibrium Green’s Function (NEGF)-Poisson quantum simulations, we present ${I}_{D}-!{V}_{rm GS}$ curves and band diagrams for both the devices and provide analytical justification for the observed improvement in the SS. We also study the variations in device characteristics due to the length and doping of the underlap layer in the proposed device. It is observed that an underlap length of 6 nm is optimal to achieve a low SS in the proposed device. View full abstract»

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  • Uniformity Improvement in 1T1R RRAM With Gate Voltage Ramp Programming

    Page(s): 1224 - 1226
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    Uniformity is one of the most severe challenges for resistive random access memory (RRAM). In this letter, a novel programming scheme with gate voltage ramping (GVR) is proposed to improve the uniformity of RRAM in a one transistor and one resistor structure. In traditional operation, the gate of the access transistor is biased with a constant voltage and a sweeping voltage is applied to the source or drain during the SET (from HRS to LRS) and RESET (from LRS to HRS) processes. With the GVR scheme, the gate voltage ( (V_{G}) ) is ramped and the source/drain are kept constant. A tight distribution of HRS can be achieved using GVR. Analysis of power generation in the RESET process of the GVR scheme reveals positive feedback from joule heating, which helps to accelerate filament rupture and results in a tendency to achieve full RESET. The intermediate resistance states commonly observed are effectively eliminated. View full abstract»

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  • Controllable Set Voltage in Bilayer ZnO:SiO2/ZnOx Resistance Random Access Memory by Oxygen Concentration Gradient Manipulation

    Page(s): 1227 - 1229
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    In this letter, we investigated oxygen ion concentration gradient method, which can manipulate the set voltage of zinc oxide-doped silicon oxide resistance random access memory. To analyze this method, the ITO/ZnO:SiO2/ZnOx/TiN bilayer structure was proposed and discussed. On the basis of the oxygen ions migration effect, the set voltage of the oxide-based resistive memory can be altered after a bias stress at the TiN electrode. The physical mechanism of the special resistive switching characteristics were depicted by the interaction between [O2−] gradient driving force and electrical force. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Amitava Chatterjee