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Electron Device Letters, IEEE

Issue 1 • Date Jan. 2015

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Displaying Results 1 - 25 of 34
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Electron Device Letters publication information

    Page(s): C2
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  • Changes to the Editorial Board

    Page(s): 1
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  • Study of Local Power Dissipation in Ultrascaled Silicon Nanowire FETs

    Page(s): 2 - 4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    The local electron power dissipation has been calculated in a field-effect nanowire transistor using a quantum transport formalism. Two different channel cross sections and optical and acoustic phonon mechanisms were considered. The phonon models used reproduce the phonon limited mobility in the cross sections studied. The power dissipation for different combinations of source, channel, and drain dimensions have been calculated. Due to the lack of complete electron energy relaxation inside the device, the Joule heat dissipation over-estimates the power dissipated in small nanotransistors. This over-estimation is larger for large cross sections due to the weaker phonon scattering. On the other hand, in narrow wires, the power dissipation inside the device can be large, therefore, mitigating against fabrication of very narrow nanowire transistors. We have also investigated the cooling of the device source region due to the mismatch of the Peltier coefficients between the source and the channel. View full abstract»

    Open Access
  • Fully Depleted SOI Characterization by Capacitance Analysis of p-i-n Gated Diodes

    Page(s): 5 - 7
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    Split capacitance measurements in thin SOI p-i-n gated diodes are performed and discussed. Contrarily to MOSFETs, the n+ and p+ contacts of the diode supply instantly minority and majority carriers preventing parasitic deep-depletion and transient effects. The gated diode enables accurate characterization from accumulation to strong inversion. We demonstrate that the diode capacitance curves provide extensive information, such as layer thickness and threshold voltage for both n- and p-type MOSFETs simultaneously. The experimental results are validated and explained through numerical simulations. View full abstract»

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  • Screen-Printed Si Paste for Localized B Doping in a Back Surface Field

    Page(s): 8 - 10
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    In this letter, Si paste formed by p-type Si nanoparticles (NPs) and an organic solvent is used as the source of B. Si NPs with a diameter of $sim 30$ nm are prepared using the pulsed electrical discharge method. The preprocessed Si wafers (after laser opening) are used as the substrate. Si paste with different percentages of Si NPs is screen-printed above the openings. B atoms diffuse into Si wafers through annealing. Uniform doping profiles are observed under a laser scanning microscope. The B doping is successful as evidenced by secondary ion mass spectroscopy. View full abstract»

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  • Influence of Passivation Oxide Thickness and Device Layout on the Current Gain of SiC BJTs

    Page(s): 11 - 13
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    The effect of passivation oxide thickness and layout on the current gain of SiC bipolar junction transistors is reported. Different thicknesses of plasma enhanced chemical vapor deposited (PECVD) silicon dioxide in the range 50–150 nm were deposited prior to the same annealing process in N2O, and their effect on the transistor gain was investigated for different device layouts. For a fixed device layout, $sim 60$ % higher gains were observed for oxide thicknesses ranging between 100 and 150 nm with current gains of $sim 200$ at room temperature and >100 at 300 °C. For each tested thickness of deposited oxide, device layout providing lower collector resistance achieved slightly higher gains. View full abstract»

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  • Complementary SOI MESFETs at the 45-nm CMOS Node

    Page(s): 14 - 16
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    Silicon-on-insulator (SOI) metal-semiconductor field-effect transistors (MESFETs) with complementary n- and p-type channels have been fabricated using a commercial 45-nm CMOS process. The current drive and transconductance of the n-MESFET is approximately three times larger than that of the p-MESFET due to the higher electron mobility. Both devices operate in depletion mode with the threshold voltage of the n-MESFET being approximately −0.4 V, while that of the p-MESFET is $sim 0.3$ V. The MESFETs have multiple gigahertz cutoff frequencies and can withstand drain bias in excess of 4 V making them attractive for analog- and mixed-signal applications that require higher operating voltages than the baseline CMOS. The p-MESFET has higher leakage current due to the lower Schottky barrier height to the p-type channel. View full abstract»

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  • 94-GHz Large-Signal Operation of AlInN/GaN High-Electron-Mobility Transistors on Silicon With Regrown Ohmic Contacts

    Page(s): 17 - 19
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    We report the first 94-GHz ( $W$ -band) large-signal performance of AlInN/GaN high-electron-mobility transistors (HEMTs) grown on high-resistivity silicon (111) substrates. A maximum output power density of 1.35 W/mm and peak power-added-efficiency of 12% are measured at 94 GHz. The devices exhibit a dc maximum current drain density of 1.6 A/mm and a peak transconductance of 650 mS/mm. In small-signal operation, cutoff frequencies ${f} _{rm T}/ {f} _{mathrm {MAX}}=141/232$ GHz are achieved. The large-signal performance of our AlInN/GaN HEMTs on silicon at 94 GHz stills lags the best reported results one on SiC substrates but nevertheless confirms the tremendous interest of GaN-on-Si HEMT technology for low-cost millimeter-wave electronic applications. View full abstract»

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  • 0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6 Tunnel FET

    Page(s): 20 - 22
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    In this letter, we demonstrate using fast current-voltage measurements, low switching slope of 64 mV/decade over a drain current range between $10^{mathrm {mathbf {-3}}}$ and $2 times 10^{mathrm {mathbf {-2}}} mu $ A/ $mu $ m in staggered-gap In0.65Ga0.35As/GaAs0.4Sb0.6 tunneling field-effect transistors (TFETs) at $mathrm{V}_{mathrm {mathbf {DS}}},=,0.5$ V. This is achieved through a combination of low damage mesa sidewall etch and improvement in electrical quality of the high- $kappa $ gate-stack. Benchmarking our results against experimentally demonstrated TFETs, we conclude that, the staggered-gap TFETs are capable of achieving simultaneously high drive current and low switching slope. View full abstract»

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  • Design Space of III-N Hot Electron Transistors Using AlGaN and InGaN Polarization-Dipole Barriers

    Page(s): 23 - 25
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    Transistor operation by common emitter (CE) current modulation is shown for the first time in III-N hot electron transistors (HETs). The emitter and collector barriers ( $phi _{mathrm {mathbf {BE}}}$ and $phi _{mathrm {mathbf {BC}}}$ ) are implemented using Al0.45 Ga0.55N and In0.1Ga0.9N layers as polarization dipoles, respectively. CE modulation is achieved by increasing the E-B barrier height beyond the B-C barrier height by increasing the Al0.45Ga0.55N thickness ( $t$ ). Similar CE performance is seen in the identical HET structures grown on both bulk GaN and sapphire. A maximum $alpha $ of $sim 0.3$ is achieved using a GaN base thickness of 10 nm. The InGaN dipole used as the collector barrier is shown to be instrumental in enabling ohmic base contacts, low base sheet resistance, and low collector leakage, simultaneously. View full abstract»

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  • Gate Bias Dependence of Complex Random Telegraph Noise Behavior in 65-nm NOR Flash Memory

    Page(s): 26 - 28
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    The dependence of complex random telegraph noise (RTN) behavior on gate bias is investigated. Noise-type transition among 1/ $f$ noise, two-level RTN, and three-level RTN is observed depending on the gate bias. The transition can be detected in both program and erase states and the corresponding transition voltage decreases with the increase of threshold voltage. The phenomena are interpreted by the spectroscopic analysis of process-induced trap and stress-induced trap. A three regions model is finally proposed. View full abstract»

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  • All-Metal-Nitride RRAM Devices

    Page(s): 29 - 31
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    This letter presents the novel CMOS-compatible all-metal-nitride resistive random access memory (RRAM) devices based on the TiN/AlN/TiN stack. The device has low operation current $<100 mu $ A, retention of $> 3times 10^{5}$ s at 150 °C, and ac endurance of up to $10^{5}$ Hz. The device switch characteristics are found to agree with the filamentary switch mechanism. In addition, the RRAM devices built with an additional hafnium nitride capping layer have showed less switch voltage variations and stable switch characteristics. View full abstract»

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  • Demonstration of Low Power 3-bit Multilevel Cell Characteristics in a TaOx-Based RRAM by Stack Engineering

    Page(s): 32 - 34
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    Multilevel cell (MLC) storage technology is attractive in achieving ultrahigh density memory with low cost. In this letter, we have demonstrated 3-bit per cell storage characteristics in a TaOx-based RRAM. By analyzing the key requirements for MLC operation mainly the switching uniformity and stability of resistance levels, an engineered stack based on thermodynamics in top electrode/(vacancy reservoir/defect control layer)/switching layer/bottom electrode structure was designed. In the optimized stack with $sim 10$ -nm Ta layer incorporated at W/TaOx interface, seven low resistance state levels with same high resistance state were obtained by controlling the switching current down from $30~mu $ A enabling low power 3-bit storage in contrast to the control device which shows 2-bit MLC with resistance saturation. The improved switching and MLC behavior is attributed to the minimized stochastic nature of set/reset operations due to filament confinement by favorable electric field generation and formation of thin but highly conductive filament which is confirmed electrically. View full abstract»

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  • Oxide Semiconductor Thin Film Transistors on Thin Solution-Cast Flexible Substrates

    Page(s): 35 - 37
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    We report ZnO thin-film transistors (TFTs) fabricated on solution-cast thin polyimide flexible substrates. Plasma-enhanced atomic layer deposition was used to deposit ZnO semiconductor and Al2O3 dielectric layers and the highest processing temperature used was 200 °C. The TFTs fabricated on thin polyimide substrates have characteristics very similar to devices fabricated on glass substrates and device characteristics changed little with release from the casting substrate. Typical TFT mobility was >12 $mathrm{cm}^{2}$/${rm V} cdot {rm s}$ for a gate electric field of 2 MV/cm. Released substrates with the TFTs were flexed between 3.5-mm radius and flat for 50000 cycles with little change in device characteristics. These results demonstrate solution casting of thin polymer layer substrates as a simple path to oxide semiconductor flexible electronics. View full abstract»

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  • Highly Stable ZnON Thin-Film Transistors With High Field-Effect Mobility Exceeding 50 $mathrm{cm}^{2}$ /Vs

    Page(s): 38 - 40
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    High-performance thin-film transistors (TFTs) based on ZnON channels were fabricated using a dc reactive sputtering method. To improve the photoinduced bias stability, a postannealing process was carried out at a low ambient pressure ( $sim 100$ mTorr, air ambient) at 250 °C for various annealing times (1–5 h). The transfer characteristics of the postannealed ZnON TFTs exhibited an improved subthreshold swing ranging from 0.60 to 0.42 V/decade. Other transport properties remained similar including a high mobility ( $mu _{rm sat}$ ) of >50 $mathrm{cm}^{2}$ /Vs, a threshold voltage ( $V_{rm th}$ ) of −2.5 V, and an ON-OFF drain current ratio of $> 10^{8}$ . In addition, photoinduced bias reliability under a gate bias stress ( $V_{G} = -20$ V) was significantly improved from −10.88 V (1 h) to −2.28 V (5 h). These results can be explained by the enhancement of bonding properties between Zn metal and two different anions (O, N) as stable N–Zn–O states. View full abstract»

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  • A $alpha $ -Si:H Thin-Film Phototransistor for a Near-Infrared Touch Sensor

    Page(s): 41 - 43
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    This letter presents a highly sensitive near-infrared (IR) $a$ -Si:H phototransistor for touch sensor applications. The narrow bandgap of $a$ -Si exhibits a wideband spectrum response from IR to ultraviolet region, where the IR bandpass filter layers allow the $a$ -Si:H phototransistor to respond to the selective IR light uninterrupted by visible light. The time-resolved photoresponse and transfer $I$ $V$ characteristics for the near-IR $a$ -Si:H phototransistor as a function of power at 785-nm illumination allow the observation of fast photoresponse ( $tau sim 0.1$ ps), high external quantum efficiency (7.52), and high photoresponse. A prototype unit pixel structure for touch sensors composed of amorphous Si-based switching/amplification/near-IR phototransistors and a storage capacitor, is proposed and designed. The overall results suggest that the near-IR $a$ -Si:H phototransistor offers unique possibilities for user-friendly, low-cost, and large-area touch sensors, especially aimed at consumer applications and other areas of optoelectronics. View full abstract»

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  • High-Responsivity and High-Sensitivity Graphene Dots/a-IGZO Thin-Film Phototransistor

    Page(s): 44 - 46
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    An a-IGZO thin-film phototransistor incorporating graphene absorption layer was proposed to enhance the responsivity and sensitivity simultaneously for photodetection from ultraviolet to visible regime. The spin-coated graphene dots absorb incident light, transferring electrons to the underlying a-IGZO to establish a photochannel. The 5 A/W responsivity and 1000 photo-to-dark current ratio were achieved for graphene phototransistor at 500 nm. As compared with <1% absorption, the graphene phototransistor indicates a >2700 transistor gain. The highest responsivity and photo-to-dark current ratio is 897 A/W and $10^{6}$ , respectively, under 340-nm light illumination. View full abstract»

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  • New Superjunction LDMOS Breaking Silicon Limit by Electric Field Modulation of Buffered Step Doping

    Page(s): 47 - 49
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    A new superjunction LDMOS (SJ-LDMOS) is proposed with the step doping buffered layer under the SJ layer to obtain the low loss for the high-voltage region. The substrate-assisted depletion effect, which results from the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the step doping buffer layer. By the effect of the electric field modulation, a more uniform lateral electric filed is obtained due to the new high-electric field peaks introduced by the buffered step doping, which improves the breakdown voltage (BV) and average lateral electric field. Using ISE simulation, the BV of proposed SJ-LDMOST is increased by $sim 50$ % than that of the conventional LDMOS, and improved by $sim 32$ % than that of buffered SJ-LDMOS. The lateral average electric field is increased to 19 V/ $mu $ m in the high-voltage region The experimental ${R} _{mathbf {mathrm{{scriptstyle ON}},{textrm sp}}}$ of the proposed SJ-LDMOS is 241 m $Omega ,cdot $ $mathrm{cm}^{mathrm {mathbf {2}}}$ with a BV of 368 V, breaking the silicon limit relationship for ${R} _{mathrm{{scriptstyle ON}},textrm {sp}}$ of 71.8 m $Omega ~cdot ~mathrm{cm}^{mathrm {mathbf {2}}}$ with the BV of 242 V in the conventional LDMOS with the same drift region length The merit of BV/ $R _{mathrm{{scriptstyle ON}},textrm {sp}}$ is - 5.3 for the proposed SJ-LDMOS compared with that of 3.4 for the conventional LDMOS. View full abstract»

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  • Fabrication of a Hybrid Carbon-Based Composite for Flexible Heating Element With a Zero Temperature Coefficient of Resistance

    Page(s): 50 - 52
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    We report on a hybrid carbon-based composite for zero temperature coefficient of resistance (TCR) heating element, forming edge-island type composite comprised of carbon nanotubes (CNTs) and carbon blacks (CBs) with a polydimethylsiloxane. The island-shaped CB composite is placed between a copper connection electrode and the CNT composite, acting as both a buffer and distribution layer against current flow for a zero TCR. The degree of control over this zero TCR was characterized by examining the thickness ratio between the CNT and CB layers. The optimized edge-island composite structure showed a constant normalized resistance (with <3% deviation) to 200 °C with a rapid heating property. This edge-island composite structure could be widely used for heat-related or sensor applications, solving safety, and accuracy issues. View full abstract»

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  • Extraction of Interface Trap Density in the Region Between Adjacent Wordlines in NAND Flash Memory Strings

    Page(s): 53 - 55
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    A new method to extract the interface trap density ( ${N} _{mathrm {mathbf {it}}}$ ) on the surface of the Si region between adjacent wordlines (WLs—called space region) in nand flash devices is presented in this letter. The $boldsymbol {N} _{mathrm {mathbf {it}}}$ is successfully extracted by applying charge pumping (CP) method, TCAD simulation, and modified equations. The CP current ${I} _{mathrm {mathbf {CP}}}$ of single WL and electrically tied two WLs are measured using fixed-base CP measurement as a function of pass bias. In addition, an effective space area for CP is extracted by TCAD simulation, and the equation, which is used to extract $boldsymbol {N} _{mathrm {mathbf {it}}}$ , is modified to extract separated $boldsymbol {N} _{mathrm {mathbf {it}}}$ s in the channel and the space regions. We confirm that our method is accurate by comparing the measured $boldsymbol {I} _{mathrm {mathbf {CP}}}$ with the calculated one. View full abstract»

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  • A Geometry Scalable Model for Nonlinear Thermal Impedance of Trench Isolated HBTs

    Page(s): 56 - 58
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    This letter presents a geometry scalable approach for the calculation of temperature dependent thermal impedance ( $Z_{mathbf {TH}}$ ) in trench-isolated heterojunction bipolar transistors. The model is capable of predicting the $Z_{mathbf {TH}}$ at any desired temperature and bias points. The temperature dependency is derived by discretizing the heat flow region into $n$ number of elementary slices depending on the thermal gradient. Temperature dependent thermal resistances $R_{mathbf {th}}$ s and capacitances $C_{mathbf {th}}$ s for each of the slices are calculated in a self-consistent manner. Finally, the proposed model is validated with low-frequency measurements at different ambient temperatures ( $T_{mathbf {amb}}$ ) for different transistor geometries and found to be in good agreement. View full abstract»

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  • Top-Gate Dry-Etching Patterned Polymer Thin-Film Transistors With a Protective Layer on Top of the Channel

    Page(s): 59 - 61
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    Photolithographic and dry-etching processes are developed to pattern the organic semiconductor (OSC) layer for top-gate organic thin-film transistors (OTFTs). A fluorine polymer layer is used to protect the OSC surface from the patterning processes so that the common photoresist can be used. The ON/OFF-current ratios of the patterned OTFTs are improved by about one order of magnitude compared with that of unpatterned devices. However, it is shown that removing the polymer protective layer can cause degraded subthreshold behavior due to increased interface trap density at the semiconductor/dielectric interface. A process without removing the polymer protective layer is thus developed to address this issue, and is shown to be able to provide a reliable route to achieve patterned top-gate OTFTs with high ON/OFF-current ratio, small subthreshold swing, and negligible hysteresis. View full abstract»

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  • Frequency-Modulated Lorentz Force Magnetometer With Enhanced Sensitivity via Mechanical Amplification

    Page(s): 62 - 64
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    This letter presents a micromachined silicon Lorentz force magnetometer, which consists of a flexural beam resonator coupled to current-carrying silicon beams via a microleverage mechanism. The flexural beam resonator is a force sensor, which measures the magnetic field through resonant frequency shift induced by the Lorentz force, which acts as an axial load. Previous frequency-modulated Lorentz force magnetometers suffer from low sensitivity, limited by both fabrication restrictions and lack of a force amplification mechanism. In this letter, the microleverage mechanism amplifies the Lorentz force, thereby enhancing the sensitivity of the magnetometer by a factor of 42. The device has a measured sensitivity of 6687 ppm/(mA $cdot $ T), which is two orders of magnitude larger than the prior state-of-the-art. The measured results agree with an analytical model and finite-element analysis. The frequency stability of the sensor is limited by the quality factor ( ${Q}$ ) of 540, which can be increased through improved vacuum packaging. View full abstract»

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  • Object-Property-Based Differential Eddy Current Gap Sensing Device

    Page(s): 65 - 67
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    To improve the sensitivity of thin eddy current device to measure the gap in small interlayer structure, an object-property-based differential structure is designed. The object-property-based differential eddy current gap sensing device has negative lift-off effect element (NLOEE) and positive lift-off effect element (PLOEE). The object in NLOEE/PLOEE is made of soft-magnetic material/nonmagnetic or hard-magnetic material, which results in a reduction/an increase of the NLOEE/PLOEE coil inductance with the increaese of the lift-off. Through using NLOEE and PLOEE as the neighboring arms of an electrical bridge, the conversion from the lift-off to the voltage is realized. The results show that the sensitivity can be improved using the object-property-based differential structure. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Amitava Chatterjee