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Electron Device Letters, IEEE

Issue 2 • Date Feb. 2015

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Displaying Results 1 - 25 of 47
  • Table of contents

    Page(s): C1 - 86
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    Freely Available from IEEE
  • IEEE Electron Device Letters publication information

    Page(s): C2
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    Freely Available from IEEE
  • High-Q MOS Varactors for Millimeter-Wave Applications in CMOS 28-nm FDSOI

    Page(s): 87 - 89
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    Accumulation MOS varactors on the low-power CMOS 28-nm fully depleted silicon on insulator (FDSOI) are presented with a minimum gate length of 43 nm. This process enable to improve the varactors quality factor (Q-factor) at high frequency, which can be employed for CMOS-based millimeter-wave (MMW) applications. Measured results up to 110 GHz show relatively high Q-factor close to 10 and relatively low series resistance for a conventional multifinger MOS varactors. The proposed MOS varactor is expected to improve the overall Q-factor of the inductor capacitor resonator (LC) tank of MMW oscillators. View full abstract»

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  • Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor With 36 V Breakdown Integrated in BiCMOS at Zero Cost

    Page(s): 90 - 92
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    A novel double-emitter horizontal current bipolar transistor (HCBT) with reduced-surface-field (RESURF) region is presented. The structure is integrated with standard 0.18- $mu $ m CMOS, together with high-speed HCBT with $BV_{mathbf {CEO}}=3.6$ V and double-emitter HCBT with $BV_{mathbf {CEO}}=12$ V. The second RESURF drift region is formed using a standard CMOS p-well implant for the formation of local substrate below the extrinsic collector. Collector-emitter breakdown is completely avoided by the E-field shielding. Breakdown occurs between the collector and the substrate and equals 36 V. The transistor is fabricated in HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks. View full abstract»

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  • Si-Based MOSFET and Thin Film Transistor Prepared via Hot Wire Implantation Doping Technique

    Page(s): 93 - 95
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    The silicon metal-oxide–semiconductor field-effect transistor (MOSFET) prepared via a hot wire implantation doping technique is reported in this letter. Auger electron spectroscopy results indicate that the junction depth of the phosphorus was $sim 80$ nm. It was also found that the carrier concentration of the phosphorus was $sim 5.83 times 10^{mathrm {mathbf {20}}}~mathrm{cm}^{mathrm {mathbf {-3}}}$ , as determined using from room-temperature Hall measurements. For the MOSFET device, experimental results showed drain current-drain voltage ( $I_{D}$ $V_{D}$ ) characteristics of the device measured in the dark. The transistor exhibits standard saturation and pinch-off characteristics, indicating that the entire channel region under the gate metal can be completely depleted. The technique can also be applied to thin-film transistors. View full abstract»

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  • Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs

    Page(s): 96 - 98
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    We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. The method is based on the modulation of the parasitic bipolar effect by back-gate biasing. The bipolar gain can be determined for each transistor, without the need to compare the long and short devices. The proposed method is validated by experimental data and numerical simulations. View full abstract»

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  • Feasibility Study of Semifloating Gate Transistor Gamma-Ray Dosimeter

    Page(s): 99 - 101
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    The feasibility study of semifloating gate (SFG) transistor dosimeter consisting a large area p-i-n diode between floating gate and drain region is described. No bias is applied during irradiation. The SFG is charged via the diode when exposed to gamma rays, and reset with the diode positively biased. A comprehensive device simulation that includes the mechanism of charge collection, the operation of device’s threshold voltage ( $V$ th) reading, and the effect of diode dark current have been carried out with sentaurus TCAD. As a result, high linear dependence of the $V$ th on the absorbed dose of ionizing radiation is observed with a sensitivity of 65.8 mV/Gy, which suggests that this device could be used as a sensitive gamma-ray dosimeter. View full abstract»

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  • Conductance Along the Interface Formed by 400 °C Pure Boron Deposition on Silicon

    Page(s): 102 - 104
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    The conductance along the interface between an as-deposited pure boron layer and n-type Si, fabricated at 400 °C, is found to be reliably formed with high-ohmic sheet resistance values going from $sim 30$ k $Omega $ /sq to 1 M $Omega $ /sq, depending on the exact substrate doping and biasing. The temperature coefficient is negative. It is proposed that this behavior is due to an interface monolayer of electron-filled acceptor states attracting an inversion layer of holes that provide ideal p+n junction behavior and lateral carrier transport unperturbed by interface defects. View full abstract»

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  • Low-Temperature Microwave Annealing for Tunnel Field-Effect Transistor

    Page(s): 105 - 107
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    Unlike the high-temperature activation of dopants, such as rapid thermal annealing (RTA), the activation of dopants by low-temperature microwave annealing (MWA) suppresses their diffusion, reducing screening tunneling length ( $lambda $ ). This letter compares low-temperature (490 °C) MWA with high-temperature (1050 °C) RTA of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field-effect transistor (TFET). The band-to-band tunneling voltage ( $mathrm{V}_{mathrm {mathbf {BTBT}}}$ ) indicates clearly that TFET annealed by MWA had a lower $lambda $ than TFET that was annealed by RTA. The TFET that was annealed by MWA had a high ON/OFF current ratio of $10^{mathrm {mathbf {8}}}$ , a low subthreshold swing, and an almost negligible drain-induced barrier lowering. View full abstract»

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  • An Explicit Surface Potential Calculation and Compact Current Model for AlGaN/GaN HEMTs

    Page(s): 108 - 110
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    In this letter, a new compact model for the AlGaN/GaN high-electron mobility transistors developed based on explicit solutions to the Fermi level and the surface potential is presented. Its simple calculation and high accuracy in predicting the surface potential and current–voltage characteristics make the model ideal for circuit simulation applications. This surface-potential-based compact model accounts for the self-heating effect by considering the temperature-dependent free-carrier mobility. The model is verified against numerical results and measured data under a wide range of bias conditions. View full abstract»

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  • Electrothermal Mapping of AlGaN/GaN HEMTs Using Microresistance Thermometer Detectors

    Page(s): 111 - 113
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    Self-heating effects in AlGaN/GaN high-electron mobility transistors (HEMTs) can notably reduce electron mobility and produce reliability concerns. Electrothermal characterization and appropriate thermal management are required to address this situation. This letter presents the measurement of channel temperature ( $mathbf {T_{ch}}$ ) of GaN HEMTs in multiple bias conditions with a good accuracy. The measurements are executed using the integrated microresistance thermometer detector ( $mu $ RTD) technique in AlGaN/GaN HEMTs on SiC and sapphire substrates. The integrated Ti/Pt $mu $ RTD sensor with linear resistance-temperature characteristic is used to obtain an ${I_{rm ds}}$ ${V_{rm ds}}$ ${T_{rm ch}}$ map for each device. Thermal resistances are compared for similar operation conditions, obtaining ${R_{rm TH} = 34.7}, {mathrm { {^{circ }}{mathbf{C}} boldsymbol {cdot } {mathbf{W}}^{-{mathbf{1}}} }}$ for the HEMT on SiC and ${R_{ rm TH} = 157.2}~ {mathrm { {^{circ }}{mathbf{C}} boldsymbol {cdot } {mathbf{W}}^{-{mathbf{1}}} }}$ for the HEMT on sapphire. View full abstract»

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  • Mobility and Capacitance Comparison in Scaled InGaAs Versus Si Trigate MOSFETs

    Page(s): 114 - 116
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    In this letter, we study the electronic properties of InGaAs and Si trigates using the nonparabolic effective mass approximation and up-to-date mobility models. Our comprehensive simulations estimate a strong reduction of the InGaAs electron mobility to values even lower than those achieved with Si. Considering the reduction of the gate capacitance due to the low density-of-states of the III-V alloy, no apparent benefit would be obtained from using InGaAs trigates instead of Si ones unless high quality interfaces can be achieved. We conclude that the potential application of InGaAs trigates as a reference device for future technological nodes is seriously jeopardized by the quality of the semiconductor-insulator interface. View full abstract»

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  • Impact of Sidewall Passivation and Channel Composition on InxGa1-xAs FinFET Performance

    Page(s): 117 - 119
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    We experimentally demonstrate InxGa1-xAs FinFET devices with varying indium composition and quantum confinement effect. While increasing indium content enhances drive current by increasing the injection velocity, increasing quantum confinement enhances the drive currents by significantly improving the short-channel effects. Further, improved sidewall passivation using an in situ plasma nitride passivation process provides additional improved subthreshold behavior. Competitive drive currents are obtained with FinFETs realized through a scaled fin pitch process allowing 10-fins/ $mu $ m layout width at a fin width of 20 nm. We report field effect mobility from multifin split-capacitance-voltage (split-CV) measurements having peak mobility of 3480 $mathrm{cm}^{2}$ /V $cdot $ s for a 10-nm QW FinFET with 70% indium. Peak transconductance ( $g_{rm mmax}$ ) of 1.62 mS/ $mu $ m, normalized to circumference, is demonstrated for devices with $L_{G}=120$ nm. View full abstract»

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  • Impact of Varying Indium(x) Concentration and Quantum Confinement on PBTI Reliability in InxGa1-xAs FinFET

    Page(s): 120 - 122
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    In this letter, we present a comparative study of positive bias temperature instability (PBTI) reliability in InxGa1-xAs FinFET with varying Indium ( $x=0.53$ , 0.70) percentage and quantization [bulk, quantum well (QW)]. Due to lower effective transport mass and higher injection velocity, In0.7Ga0.3As QW FinFET provides better performance than In0.53Ga0.47As bulk FinFET. However, stronger quantization lowers the effective barrier height between the carriers and defect density in the oxide causing degraded PBTI reliability in the former. Our preliminary PBTI stress study shows that In0.7Ga0.3As QW FinFETs may need to operate at a gate overdrive of 0.1 V (i.e., near threshold operation) to meet 10 years of reliability specifications at 85 °C. View full abstract»

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  • High-Frequency Performance of GaN High-Electron Mobility Transistors on 3C-SiC/Si Substrates With Au-Free Ohmic Contacts

    Page(s): 123 - 125
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    As an alternative to the standard Au-based ohmic contacts, in this letter, Ti/TiN contacts were used to fabricate GaN high-electron mobility transistors (HEMTs) with two barrier designs (Al0.2Ga0.8N/AlN and Al0.35wGa0.65N). The ohmic contact resistance for this Au-free metallization scheme with a very smooth surface morphology is $0.13~Omega $ mm and the specific contact resistance is $sim 10^{mathrm {mathbf {-6}}}~Omega $ $mathrm{cm}^{mathrm {mathbf {2}}}$ . Our best 100-nm gate transistors show a maximum drain current density of 1.13 A/mm and a peak extrinsic transconductance of 388 mS/mm. The fastest transistors with a gate length of 80-nm achieve cutoff frequencies of 176 GHz, rivaling the fastest GaN HEMTs on silicon and silicon carbide substrate with comparable gate length and Au-based ohmic contacts. View full abstract»

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  • Nanoscale Mo Ohmic Contacts to III–V Fins

    Page(s): 126 - 128
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    A novel contact-first approach for III–V FinFETs and trigate MOSFETs is presented. In this process, the metal contact is sputtered on the as-grown semiconductor heterostructure, and the contact metal is used as a part of the fin dry-etch mask. We demonstrate this technique in Mo/n+-InGaAs contact structures with fin widths in the range of 50 to 300 nm. We have measured contact resistance in the range of 5 to $20~Omega ,cdot ,mu $ m. These results are in good agreement with the state-of-art contact resistance obtained on planar devices using similar technology. We further explore the possibility of enhancing the contacts by wrapping the metal over the fin sidewalls and found no significant improvement. View full abstract»

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  • Superior Retention of Low-Resistance State in Conductive Bridge Random Access Memory With Single Filament Formation

    Page(s): 129 - 131
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    Data retention is one crucial reliability aspect of resistive random access memory (RRAM). The retention failure mechanism of the low-resistance state (LRS) for conductive bridge RAM is generally originated from the lateral diffusion of metal ions/atoms from the filament to its surrounding medium. In this letter, we proposed an effective method to improve the LRS retention by controlling the formation of the single filament. For a certain LRS, the effective surface area for metal ions/atoms diffusion in single filament is less than that of multi-filament. Thus, better LRS retention characteristics can be achieved by reducing the metal species diffusion. The validity of this method is verified by the superior retention characteristics of the LRS programmed by current mode, in comparison with voltage programming mode. The former tends to generate a single filament, while the later grows multi-filament. This letter provides a possible way to enhance the retention characteristics of RRAM. View full abstract»

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  • First Detection of Single-Electron Charging of the Floating Gate of NAND Flash Memory Cells

    Page(s): 132 - 134
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    This letter provides the first direct experimental detection of single-electron charging of the floating gate of a mainstream Flash memory cell. The detection is shown to be easily achievable through conventional and very simple measurement techniques on state-of-the-art technologies. Results represent a milestone for the investigation of the physics of Flash memory operation, opening the possibility for direct analyses of the piling up of single electrons in the floating gate during cell programming. View full abstract»

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  • Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory

    Page(s): 135 - 137
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    A new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. This abrupt degradation is believed due to the creation of a new soft breakdown path in a switching dielectric by cycling stress. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. This cycling-induced degradation mode imposes a serious constraint on the number of SET-disturb pulses and thus an endurance cycle number in a resistive switching memory. View full abstract»

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  • Utilizing the Variability of Resistive Random Access Memory to Implement Reconfigurable Physical Unclonable Functions

    Page(s): 138 - 140
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    The stochastic switching mechanism and intrinsic variability of resistive random access memory (RRAM) present severe challenges for memory applications, which, however, may be utilized to implement the physical unclonable function (PUF) for hardware security. A PUF based on RRAM resistance variability is proposed in this letter. Unlike PUFs based on manufacturing variation, this proposal exploits an intrinsic variability in physical mechanisms with reconfigurability. Key characteristics of the PUF design are assessed by simulation using measured RRAM properties and device model. Truly random variation of RRAM resistance is critical for PUF uniqueness (or unclonability). The reliability (or robustness) of the proposed PUF is affected by temperature and voltage dependence of RRAM resistance as well as retention characteristics. Large separation between inter-chip and intra-chip Hamming distance as the measure of uniqueness and reliability confirms the feasibility of the PUF proposal. View full abstract»

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  • Significant Reduction of Dynamic Negative Bias Stress-Induced Degradation in Bridged-Grain Poly-Si TFTs

    Page(s): 141 - 143
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    The device degradation of bridged-grain (BG) polycrystalline silicon thin-film transistors under dynamic negative bias stress (NBS) is investigated for the first time. By employing a BG structure in the active channel, dynamic NBS-induced hot carrier degradation could be significantly reduced from −99.9% to −2.4% ( $10^{mathrm {mathbf {4}}}$ s dynamic NBS), which is attributed to a sharing of the lateral electric field across the multiple p-n junctions inherent in the structure. The nonequilibrium junction degradation model is employed and developed, incorporated with TCAD simulations. View full abstract»

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  • Dual-Sweep Combinational Transconductance Technique for Separate Extraction of Parasitic Resistances in Amorphous Thin-Film Transistors

    Page(s): 144 - 146
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    We report a dual-sweep combinational transconductance technique for separate extraction of parasitic source ( ${R}_{S}$ ) and drain ( $R_{D}$ ) resistances in thin-film transistors (TFTs) by combining forward and reverse transfer characteristics. In the proposed technique, gate bias-dependent total resistance [ $R_{rm TOT}$ ( $V_{rm GS}$ )] and degradation of the transcond- uctance due to the parasitic resistance at the source terminal during the dual-sweep characterization are employed. Applying the proposed technique to amorphous oxide semiconductor TFTs with various combinations of channel length ( ${L}$ ) and width ( $W$ ), we successfully separated $R_{S}$ and $R_{D}$ . A model for the $W$ - and $L$ -dependences of the extracted parasitic resistances is also provided. View full abstract»

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  • High Performance of Self-Aligned Transparent Polysilicon-Gate Thin-Film Transistors by NiSi2 Seed-Induced Lateral Crystallization

    Page(s): 147 - 149
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    A heavily doped p-type polysilicon (poly-Si)-gate thin-film transistors using NiSi2 seed-induced lateral crystallization (SILC) were successfully developed for the transparent electronic device. The hydrogenated amorphous-silicons of gate and active layer were laterally crystallized and doped with B2H6 in self-aligned structure. The average transmittance of SILC poly-Si film showed 68% in the visible spectrum because of its 98% of crystalline volume fraction ( $chi ^{c}$ ). Comparing with the metal-induced crystallized poly-Si poly-Si-gate, the electrical performance of the leakage current and threshold voltage was improved. View full abstract»

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  • Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure

    Page(s): 150 - 152
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    Ultrathin channel trench junctionless poly-Si field-effect transistor (trench JL-FET) with a 2.4-nm channel thickness is experimentally demonstrated. Dry etching process is used to form trench structures, which define channel thickness ( $T_{mathrm {CH}})$ and gate length ( $L_{G})$ . These devices ( $L_{G}= 0.5 mu $ m) show excellent performance in terms of steep subthreshold swing (100 mV/decade) and high $I_{mathrm{{scriptstyle ON}}}/ I_{mathrm{{scriptstyle OFF}}}$ current ratio ( $10^{6}$ A/A) and practically negligible drain-induced barrier lowering ( $sim 0$ mV/V). The $I_{rm mathrm{{scriptstyle ON}}}$ current of the trench JL-FET can be further increased by the quantum confinement effect. Importantly, owing to its excellent device characteristics and simplicity of fabrication, the trench JL-FET has great potential for using in advanced 3-D-stacked IC applications. View full abstract»

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  • High-Speed Pseudo-CMOS Circuits Using Bulk Accumulation a-IGZO TFTs

    Page(s): 153 - 155
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    We propose a way to achieve high-speed circuits with dual-gate (DG) bulk-accumulation back-channel-etched (BCE) amorphous indium-gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) using the pseudo-CMOS structure. The DG BCE a-IGZO TFTs exhibit field-effect mobility ( $mu _{mathrm {mathbf {FE}}}$ ), threshold voltage ( $V_{mathrm {mathbf {th}}}$ ), and subthreshold swing of 30 ± 3 $mathrm{cm}^{mathrm {mathbf {2}}}$ /Vs, 2 ± 0.5 V, and 120 ± 30 mV/decade, respectively. For input voltage ( $V_{mathrm {mathbf {DD}}}$ ) of 20 V, seven-stage pseudo-CMOS ring oscillators implemented with the BCE bulk-accumulation a-IGZO TFTs show oscillation frequency of 6.51 MHz, which corresponds to a propagation delay time of 11 ns/stage and is faster than the 17 ns/stage delay of the fastest single-gate-driven ratioed coplanar a-IGZO TFT circuits. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Amitava Chatterjee