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VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on

Date 26-29 April 2010

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Displaying Results 1 - 25 of 93
  • [Copyright notice]

    Publication Year: 2010 , Page(s): 1
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    Freely Available from IEEE
  • Welcome message from general Co-chairs

    Publication Year: 2010 , Page(s): 1
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  • Foreword

    Publication Year: 2010 , Page(s): 1
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  • Table of content

    Publication Year: 2010 , Page(s): 1 - 7
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  • The Exascale challenge

    Publication Year: 2010 , Page(s): 2 - 3
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2135 KB) |  | HTML iconHTML  

    Exascale performance in the next decade can be made possible by supply voltage scaling, managing concurrency and system level resiliency, thus impacting mainstream computing to deliver unprecedented compute performance. This paper describes challenges and solutions. View full abstract»

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  • K2 the changing role of test in semiconductor manufacturing

    Publication Year: 2010 , Page(s): 4
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    Test has traditionally played the role of arbiter of quality, determining as quickly as possible which devices “pass” and which are defective. However, as the gulf widens between IC design and manufacturing, and as manufacturing variability becomes more prevalent, test is being seen more as a source of valuable product data than as just a simple screening mechanism. In this talk we will examine some of the ways in which test is forming a stronger link between VLSI design and manufacturing. View full abstract»

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  • K3 Moore's Law in the Era of GPU Computing

    Publication Year: 2010 , Page(s): 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (138 KB) |  | HTML iconHTML  

    The history of humanity is that we strive to use better tools and knowledge to build even better tools, and extend further the border of knowledge. In the past 50 years, CPU, as a dominant paradigm for computing, has provided exponential growth as predicted by Moore's Law with remarkable accuracy. We have been leveraging CPUs to design future CPUs. However, we believe that CPU has exhausted its potential, and the growth has plateauded. CPU is relaying momentum to the next paradigm, GPU. We are entering the Era of GPU Computing, where the exponential growth continues at a higher emergent level. View full abstract»

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  • Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

    Publication Year: 2010 , Page(s): 7 - 10
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (426 KB) |  | HTML iconHTML  

    Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2μm) tungsten (W) film, W-fill TSV, and surrounding silicon structures, using Flexus bowing measurement, Wright etch method, and also 3-D TSV stress simulations. In this study, the stress was found to be primarily tensile, and tended to be much higher along the longitudinal ends of the TSV compared to the longitudinal side wall. For an isolated TSV of given width and depth: with 30 μm length the stress is 45% greater compared to the case of 7 μm length. For an array of TSV with given length, width, and depth: larger spacing along the longitudinal axis (length directions) resulted in 35% lower stress at the longitudinal ends of the TSV, while smaller spacing along the transverse axis (width directions) of the TSV resulted in a 46% lower tensile stress. However, along the longitudinal side walls, the tensile stress increases by 200 MPa as the spacing along the transverse axis decreases between neighboring TSV. View full abstract»

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  • 3D integration technology for energy efficient system design

    Publication Year: 2010 , Page(s): 11 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (831 KB) |  | HTML iconHTML  

    CMOS scaling will continue, doubling transistor integration capacity every two years, providing billions of transistors to enable future novel systems. 3D integration technology will open the doors even further, changing the landscape and allowing integration of diverse functionality to realize energy-efficient and affordable complex systems that will continue to deliver higher performance. This paper presents how to exploit this new technology for energy efficient system design. View full abstract»

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  • Verifying thermal/thermo-mechanical behavior of a 3D stack - challenges and solutions

    Publication Year: 2010 , Page(s): 15 - 16
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (410 KB) |  | HTML iconHTML  

    The paper describes the design challenges for a low-cost 3D Cu-TSV technology. Based on experimental characterization, we'll indicate the importance of thermal and thermo-mechanical challenges. To avoid related yield loss and/or reliability issues, thermo-mechanical and thermal hotspots should be re-solved in early phases of the design flow. We will present a possible design flow hereto based on the concept of “smart mechanical samples”. View full abstract»

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  • Via mid through silicon vias - the manufacturability outlook

    Publication Year: 2010 , Page(s): 17 - 18
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    The potential for via-mid through-silicon vias (TSVs) can be considerable, since their use allows not only a reduction in interconnect length from several mm to several microns, but also a tremendous increase in bandwidth between the stacked chips. The net result is less power consumption, higher performance, increased device density within a given chip footprint, and greater potential to integrate diverse technologies at an overall lower cost. This presentation will cover the manufacturability outlook for via-mid TSVs including equipment, process, and metrology maturity. View full abstract»

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  • ThruChip interface for 3D system integration

    Publication Year: 2010 , Page(s): 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB) |  | HTML iconHTML  

    ThruChip Interface (TCI) employing inductive coupling bares comparison with Through Silicon Via (TSV) in terms of data rate (11Gb/s/ch), reliability (BER≪10-14), and energy dissipation (0.14pJ/b). It is less expensive than TSV by 20c/chip, though, since it is implemented by digital circuits in a standard CMOS. ESD protection devices can be eliminated to further lower delay, power, and area. It exhibits high noise immunity and alignment tolerance. It provides with an AC coupling link to make interface design easy under multiple/variable VDD's. The cost/performance will further be improved exponentially by thinning chip thickness. Applications include Solid-State Drive (SSD) by stacking NAND Flash memories, a high-speed low-power DRAM interface, bus probing through package for debugging, and non-contact wafer testing. Wireless power delivery by using inductive coupling will further widen the applications. This talk will cover basics, applications, and future perspectives of the TCI. View full abstract»

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  • Real-time hierarchical bus system with Static arbitration using timer-controlled Priority Allocator for a multi-media SoC

    Publication Year: 2010 , Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    Latest multi-media SoCs used in a digital product such as digital TV have a structure where a number of IPs with real-time requirement share one channel of off-chip SDRAM using high-frequency bus to achieve multi-function, high-performance, and low-cost. Thus, such a bus system is required that satisfies real-time requirement, realizes high-efficiency, and has hierarchical structure. In this bus system, bus arbitration plays a crucial role. In this paper, we show Static arbitration has an advantage in bus efficiency over existing arbitration algorithms. And we propose a real-time hierarchical bus system with Static arbitration using timer-controlled Priority Allocator and the Priority Level Transmission Mechanism. Simulation results show that the proposed bus system can satisfy real-time requirement, and is practical and efficient. View full abstract»

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  • Exploring parallelism during processor design space exploration

    Publication Year: 2010 , Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    To exploit the spatial parallelism within target applications, various processor architectures are proposed. However, to estimate the scope of parallelism from high-level application remains a daunting task. A re-targetable as well as efficient High-Level Language (HLL) compiler is needed for that purpose. Building such a compiler in the early phase of processor modeling is extremely difficult. This paper proposes efficient techniques to uncover fine-grained and coarse-grained parallelism opportunities in a processor without depending on advanced compiler support. The techniques are built upon an Architecture Description Language (ADL)-driven processor exploration framework, which gives feedback to the designer on various performance aspects in the design exploration phase. Experimental studies with modern embedded applications are presented to validate the importance of this work. View full abstract»

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  • A configurable SystemC virtual platform for early software development and its sub-system for hardware verification

    Publication Year: 2010 , Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (346 KB) |  | HTML iconHTML  

    System-on-chips (SoCs) for modern embedded systems are becoming more and more complex, together with the short time to market demand are challenging the current hardware and software development methodology, which has been driving recent ESL methodology development in the industry. In this paper, we introduce a SystemC virtual platform for early software development. A sub-system of the virtual platform is also introduced to accelerate the verification of hardware modules. View full abstract»

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  • Platform-based design automation - Platform Core Compiler

    Publication Year: 2010 , Page(s): 33 - 35
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (190 KB) |  | HTML iconHTML  

    A platform-based design automation methodology is described. The methodology brings advantages that include supporting configurable platform architecture, improving quality of SoC integration and avoiding manual error and shorten SoC integration schedule. A benchmark is also proposed to realize how the methodology can address the targets and meet time-to-market goal. View full abstract»

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  • Efficient LDPC decoder implementation for DVB-S2 system

    Publication Year: 2010 , Page(s): 37 - 40
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    Low Density Parity Check (LDPC) codes have been adopted in many communication standards in recent years due to their Shannon limit approaching performance. More than that, many standards adopt long block length LDPC codes to achieve better performance. Calculation units are, therefore, increased significantly. Traditional simplified algorithm is not suitable for cutting edge transmission of high quality multimedia data because of the serious performance degradation. Better performance with minimum compensation architecture must be realized. This paper is to present the compensation architecture with minimum added circuits. View full abstract»

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  • Design of a digital power IC

    Publication Year: 2010 , Page(s): 41 - 44
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (237 KB) |  | HTML iconHTML  

    To satisfy today's power demands of a VLSI chip, the digital power IC has been designed in order to have more programmability, faster transient response and higher efficiency. Thank to the advance of the semiconductor manufacturing process. It has enabled the ability to integrate the power MOSFET, the analog and the digital circuits into one chip. In this paper, a 12V, 2A digital synchronous DC-DC buck converter IC with the nonlinear control (NLC) to improve the transient response and the pulse-skipping mode (PSM) to improve the power conversion efficiency has been designed and fabricated. The I2C is provided to let the host controller in-situ program and monitor the operating conditions of the IC. Both the loading current and the operating mode transient response of the IC have been demonstrated. View full abstract»

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  • A novel dynamic over-drive scheme for LCD with dynamic driving gamma curves

    Publication Year: 2010 , Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (958 KB) |  | HTML iconHTML  

    A novel LCD overdrive system for dynamic driving gamma curves is proposed. General gray-to-gray overdrive lookup tables can only be applied to LCDs with a fixed driving gamma curve. However, in some advanced video processing systems, dynamic driving gamma curves are necessary. Instead of the conventional gray-to-gray lookup table, a voltage-to-voltage lookup table was adopted in the proposed method. Since the voltage-to-voltage overdrive lookup table is the material characteristics of LC, which is independent from the driving gamma curve. The voltage-to-voltage overdrive table of a LC is always valid under any driving gamma curves. In the proposed system, a gray-to-voltage and another voltage-to-gray converter were used as interfaces between video input and the voltage-to-voltage overdrive table. View full abstract»

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  • Digitally-assisted analog designs for submicron CMOS technology

    Publication Year: 2010 , Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    Three different digitally-assisted analog designs are presented to demonstrate the powerful way to solve the analog design deficiencies in the submicron CMOS technology. A 200 MS/s 12-bit pipeline ADC is using the split-capacitor correlation method to solve the linear and nonlinear problems. A 1 GS/s 14-bit current-steering DAC is using the programmable sub-DAC to continuously trimming the current mismatches. A 25 MS/s 16-bit ΣΔ ADC is using the adaptive way to correct the leakage noise and DAC nonlinearity. View full abstract»

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  • A 400-MHz super-regenerative receiver with a fast digital frequency calibration

    Publication Year: 2010 , Page(s): 54 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (426 KB) |  | HTML iconHTML  

    In this work, a low-power super-regenerative receiver (SR-RX) operating in the MICS band is designed. A fast digital frequency calibration loop is proposed to adjust the oscillator center frequency to the desired frequency band and the maximum tuning time is just 2.7 μs. Some other calibration loops are also added to enhance the SR-RX performance. The SR-RX is capable of achieving a maximum data rate of 1 Mbps and, fabricated in TSMC 0.18-μm CMOS process, consumes only 2.2 mW from a 1.3-V supply voltage. View full abstract»

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  • Design challenges for sense amplifier and wireless link in high-density neural recording implants

    Publication Year: 2010 , Page(s): 61 - 64
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    In this paper we discuss the challenges in designing high-density biomedical neural implants. We discuss in more detail the constraints of the sense amplifier and the wireless link. Different techniques to design the front-end low-noise sense amplifier are discussed. We compare between different wireless designs and we show that trading off the transmitter power consumption and complexity with that of the external receiver will be mandatory to minimize the power dissipation and area of the implant. View full abstract»

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  • A wide-range all-digital delay-locked loop in 65nm CMOS technology

    Publication Year: 2010 , Page(s): 66 - 69
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (511 KB) |  | HTML iconHTML  

    An ultra wide-range delay-locked loop (DLL) has been fabricated in 65nm CMOS technology. The proposed leakage delay unit (LDU) can easily generate a large propagation delay to reduce the difficulties to build up the high-speed digital counter in the cycle-controlled delay unit (CCDU) for a very low-frequency operation. The proposed DLL circuit can operate from 500 KHz to 1 GHz, and the power consumption is 1.8mW @1GHz with very small active area (0.01mm2). View full abstract»

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  • Energy efficient bootstrapped CMOS large RC-load driver circuit for ultra low-voltage VLSI

    Publication Year: 2010 , Page(s): 70 - 73
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (543 KB) |  | HTML iconHTML  

    This paper presents an energy efficient bootstrapped CMOS driver to enhance switching speed for driving large RC load for ultra low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve more positive and negative boosted voltage levels and to allow the boosted nodes to maintain the boosted levels, thus improving boosting efficiency and enhancing the switching speed. Performance evaluation based on UMC 65nm low power technology (Vtn≈Vtp≈0.5v) indicates that the proposed driver provides rising-delay improvement of 24%-56% and falling-delay improvement of 9%-30% at Vdd = 0.3 V for 1 to 10 segments of large distributed RC loading, as compared with the conventional bootstrapped driver consuming the same power. Although designed and optimized for ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at high supply voltage as well. View full abstract»

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  • Low-Power FinFET design schemes for NOR address decoders

    Publication Year: 2010 , Page(s): 74 - 77
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption. The Low-Power (LP) scheme, a scheme where the FinFETs' back gates are reverse-biased for lower-power operation, was used as the base scheme for comparisons. The Shorted-Gate (SG) High Precharge Swing scheme has a better performance tradeoff than the other presented schemes, including the LP scheme. While dynamic power is 10.9% to 11.9% more than the LP scheme, the SG-High Precharge Swing scheme is 48.1% to 59.9% faster and dissipates 93.0% to 99.7% less leakage power than the LP scheme. In addition, the SG-High Precharge Swing scheme requires less supporting hardware as it needs one less voltage level and one less voltage conversion buffer than the LP scheme. View full abstract»

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