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VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on

Date 26-28 April 2010

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Displaying Results 1 - 25 of 74
  • Innovation in solid state devices for exascale computing

    Publication Year: 2010 , Page(s): 2 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (651 KB) |  | HTML iconHTML  

    The continuous scaling of CMOS technology has enabled system performance to double every two years for the past 40 years. However, new classes of applications will demand a much faster rate of improvement such as 2×/year in order to reach exaflop capabilities by the end of this decade. These applications represent a significant growth opportunity and require continued innovation in solid state technology including a new generation of silicon device scaling and a number of non-silicon logic switches which have been proposed as replacements. In addition, new system architectures will take advantage of 3D chip technology to enable a higher level of hybrid integration. New memory technology will allow implementation of a new level of memory architecture, while silicon nanophotonics on the processor will meet ultra-low power, low cost, and high density communications needs. These and other innovations will lead to significant improvement in systems integration, performance, and power efficiency for future applications. The roadmap that will be presented will drive semiconductor technology for decades to come. View full abstract»

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  • The technical challenges of the future generations of telecommunication technologies (LTE/4G)

    Publication Year: 2010 , Page(s): 6 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (417 KB) |  | HTML iconHTML  

    LTE applies state of the art radio, coding and protocol technologies to achieve high spectrum efficiency and communications solutions optimized for internet traffic. Multiple MIMO options, fast physical layer re-transmission solutions, faster processing requirements for low latency, and significantly higher bit rates set new challenges for hardware design. Silicon designs are pushed to develop new processing intensive solutions enabling flexibility for future feature upgrades. Advanced digital design solutions are required to meet challenges in terms of power consumption and complexity, opening an era of new innovations. We believe that the adoption will be rapid due to the flexible spectrum utilization as well as being an optimal solution for wireless broadband. LTE together with advanced silicon processes will enable a new ecosystem of wireless connectivity and applications. View full abstract»

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  • A new boom for China's semiconductor industry

    Publication Year: 2010 , Page(s): 9 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (414 KB) |  | HTML iconHTML  

    The purpose of this paper is to provide an overview of the Chinese semiconductor industry. The influence of macro environment on the world semiconductor industry after the financial crisis is analyzed. This paper points out that China will see a faster growth of the semiconductor industry with increased domestic demand and exports in the years to come. China market will play an ever more important role in the global semiconductor industry. View full abstract»

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  • Silicon millimeter-wave radios for 60 GHz and beyond

    Publication Year: 2010 , Page(s): 12 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (311 KB) |  | HTML iconHTML  

    This paper provides an overview of a 60 GHz transceiver chipset implemented in 0.12 μm SiGe BiCMOS technology, prototype 60 GHz antennas and packages developed for that chipset, and a 60 GHz phased-array receiver front-end. The transceiver chipset achieves 6 dB noise figure in the receiver and 10 dBm output compression point in the transmitter. Folded-dipole and patch antenna arrays developed for the 60 GHz chipset show >90% efficiencies and broad bandwidths. These antennas were attached to the SiGe RF chips, and the packaged chipset has been used to transmit an uncompressed high-definition video stream at 2 Gb/s, with even higher data rates possible. Finally, a 60 GHz RF-combined phased-array receiver front-end is discussed which uses a hybrid parallel/series phase-shifting architecture and which achieves full spatial coverage with reduced phase-shifter requirements. View full abstract»

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  • Silicon-based monolithic millimeter-wave integrated circuits

    Publication Year: 2010 , Page(s): 14 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (491 KB) |  | HTML iconHTML  

    The recent research results of silicon-based monolithic millimeter-wave (MMW) integrated circuits (MMICs) at National Taiwan University (NTU) are presented in this paper. Using standard MS/RF CMOS processes, many impressive results were demonstrated. Both the MMIC designs and measured performances will be described. Significant impacts are expected due to the development for future research works in the related areas. View full abstract»

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  • RF/analog and digital faceoff — friends or enemies in an RF SoC

    Publication Year: 2010 , Page(s): 19 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    With the ever-increasing functionalities of cellular smart phones and other communication systems, RF circuits at multi-GHz frequencies have recently migrated to the state-of-the-art low-cost digital CMOS processes despite their unfriendly analog design environment. The use of digital techniques to assist RF performance is becoming a common practice. However, there is a general fear that a fully integrated RF SoC containing DSPs could easily fail due to mysterious integration issues such as silicon substrate coupling. In this paper, we will visit some of the practical aspects based on the experiences of integrating the Digital RF Processor (DRP™) in the past ten years. Some conventional wisdom that is actually not wise for RF SoCs will be illustrated. As a result of the successful commercialization of DRPs, CMOS integrated radio SoCs with digitally assisted RF is proven to be one of the clever directions and has opened additional avenues toward software-defined radios. View full abstract»

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  • Leading edge foundry Si-based RF technology for wireless communication

    Publication Year: 2010 , Page(s): 21 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (462 KB) |  | HTML iconHTML  

    As CMOS technology advances with increasingly scaled-down chip size and better MOSFET performance, new challenges and opportunities are observed in the innovation and optimization of integrated RF device for state-of-the-art RF system-on-chip (RFSOC). From technology foundry's viewpoint, this paper illustrates the essence of key RF SOC active and passive devices. View full abstract»

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  • Diodes in CMOS for millimeter and sub-millimeter wave circuits

    Publication Year: 2010 , Page(s): 23 - 24
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (434 KB) |  | HTML iconHTML  

    High volume millimeter wave applications are emerging. With the speed improvement of CMOS, sub-millimeter wave operation of CMOS circuits appears to be possible. In traditional millimeter and sub-millimeter wave systems, discrete Schottky diodes are widely utilized. This paper reviews the high frequency performance of junction and Schottky diodes fabricated in CMOS without any process modification, and circuits using the diodes, as well as suggesting approaches that can improve their performance. View full abstract»

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  • Planar FDSOI technology for sub 22nm nodes

    Publication Year: 2010 , Page(s): 26 - 27
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (486 KB) |  | HTML iconHTML  

    Recent device developments and achievements have shown that undoped channel planar Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 22nm node and below. This planar option seems to be even easier than non planar FinFET devices. This paper will report the main results obtained with this technology and will compare these results with the state of the art of Bulk and FinFET technologies: electrostatic performance, drivability, variability and scalability will be presented through silicon data and TCAD analysis. Challenges with respect to Multiple VT aspects and SRAM will also be reported. View full abstract»

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  • A 30 nm gate-all-around poly-Si nano wire thin-film transistor

    Publication Year: 2010 , Page(s): 28 - 29
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    In this work, gate-all-around (GAA) poly-Si nano wire (NW) thin film transistors (TFTs) with record physical gate length of 30 nm and driving current >100 μA/μm are demonstrated. The cross section of the NW channel is as small as 35 nm × 8 nm. The tight GAA and NW structure enhances the gate potential control ability effectively, therefore, excellent short channel and narrow width behaviors can be obtained. These results reveal the possibility of three-dimensional integrated circuits. View full abstract»

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  • A compact, high-speed, and low-power design for multi-pillar vertical MOSFET's, suppressing characteristic influences by process fluctuation

    Publication Year: 2010 , Page(s): 30 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (907 KB) |  | HTML iconHTML  

    The DC and AC characteristics of the multi-pillar vertical MOSFET's have been studied, considering the silicon pillar diameter thinning cases due to the process fluctuation. In order to suppress the pillar thinning influences, the Inter Contacts design has been proposed, which can realize the compact, high-speed, low-power, and stable circuits with the multi-pillar vertical MOSFET's. View full abstract»

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  • Investigation on the effective immunity to process induced line-edge roughness in silicon nanowire MOSFETs

    Publication Year: 2010 , Page(s): 32 - 33
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1153 KB) |  | HTML iconHTML  

    The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great potential in high-performance nano-electronics applications. However, line-edge roughness (LER) induced by lithography and etching processes has become a critical concern for decananometer MOSFETs, because it does not scale accordingly with line widths. Especially, the LER of nanowires, which contains two degrees of freedom rather than one in the traditional planar devices, may have different and intriguing effect on SNWTs. Therefore, performance variation of SNWTs induced by nanowire-LER may become a great challenge to scalability and stability of SNWT-based ICs, where 2-D geometrical fluctuation becomes an even more serious problem in nano-scale. Yet, only few preliminary studies on such impact have been reported. In this paper, a full 3-D statistical investigation is performed, based on the measured LER from SEM images, to estimate the impact of nanowire-LER on SNWTs, including both DC and analog/RF performance. The results can provide guidelines for process optimization as well as robust design of SNWT-based circuits. View full abstract»

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  • Single-crystalline Ge p-channel thin-film transistors with Schottky-barrier source/drain on flexible polyimide substrates

    Publication Year: 2010 , Page(s): 34 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (589 KB) |  | HTML iconHTML  

    We fabricated the single-crystalline Ge (sc-Ge) p-channel thin-film transistors (TFTs) with Schottky-barrier source/drain (S/D) on flexible polyimide substrates by a simplified low-temperature process (≤ 250°C), which preserves the high mobility Ge channel. Adhesive wafer bonding and Smart-Cut techniques were utilized to transfer the sc-Ge thin film onto polyimide substrates. The device has a linear hole mobility of ~170 cm2V-1s-1, saturation hole mobility of ~120 cm2V-1s-1, and Ion of ~1.6 μA/μm at Vd = -1.5 V for the channel width/length = 280/15μm. View full abstract»

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  • Carbon based graphene nanoelectronics technologies

    Publication Year: 2010 , Page(s): 36 - 37
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB) |  | HTML iconHTML  

    Graphene, a two-dimensional carbon form with the highest intrinsic carrier mobility and many desirable physical properties at room temperature, is considered a promising material for ultra high speed and low power devices with the possibility of strong scaling potential due to the ultra-thin body. (Fig. 1) Here IBM reports progress in graphene nanoelectronics, synthesizing wafer-scale monolayer-controlled graphene and fabricating high-speed single atomic layer graphene FETs (GFET) with the highest value reported cut-off frequency (fT) 50 GHz, exceeding that of the same gate length Si FETs. It is achieved by improving gate oxide deposition and reducing series resistance. Systematic characterization and small-signal models enable further engineering and optimization for even higher performance. The high Ion/Ioff ratios from bi-layer graphene suggest potential not only for analog but also for logic applications. View full abstract»

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  • Reducing Rext in laser annealed enhancement-mode In0.53Ga0.47As surface channel n-MOSFET

    Publication Year: 2010 , Page(s): 38 - 39
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (467 KB) |  | HTML iconHTML  

    High mobility, narrow band gap group IV and III-V materials are strong contenders to replace strained-Si channels for logic applications beyond the 16 nm node [1-3]. While there are many research efforts evaluating III-V channels in HEMT and MOSFET forms, model based understanding and control of the FET properties such as channel mobility, series resistance, and off-state leakage are still lacking [4-8]. In this work, we address the aforementioned issues, by investigating laser annealing to control thermal budget and lower series resistance. Additionally we also report on preliminary material analysis and demonstrate the low temperature measurement to the performance of In0.53Ga0.47As MOSFETs. The electrical and material characteristics of TaN/ZrO2/In0.53Ga0.47As self-aligned n-MOSFETs with high Ion/Ioff (> 5 × 104), high mobility (~ 3000 cm /V·sec) and promise for low Rext are presented and discussed. View full abstract»

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  • A new step in GeOI pFET scaling and Off-State current reduction: 30nm gate length and record ION/IOFF ratio

    Publication Year: 2010 , Page(s): 40 - 41
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (667 KB) |  | HTML iconHTML  

    We demonstrate the shortest Ge-channel pFETs reported to date (Lg=30 nm), on Ultra Thin GeOI obtained with the Ge enrichment technique. The Ion/Ioff ratio is raised to a record value of more than 5 decades thanks to the combination of a low defectivity, a thin Ge layer, well-controlled VΛ and SCE. This ratio could be even further improved using of germanidation, raised S/D, no channel doping, and decreasing the Ge film thickness in order to operate in full depletion at shorter gate lengths. View full abstract»

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  • Impacts of multiple-gate configuration on characteristics of poly-Si nanowire SONOS devices

    Publication Year: 2010 , Page(s): 42 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB) |  | HTML iconHTML  

    In this study, we have proposed a simple but novel way to fabricate poly-Si NW-SONOS devices. With a slight modification in the fabrication procedure, three types of devices having various gate configurations (SG, ΩG, and GAA) were successfully fabricated and characterized. The experimental results unambiguously show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, highlighting the potential of such scheme for future SONOS applications. View full abstract»

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  • Self-aligned shallow trench isolation recess effect on cell performance and reliability of 42nm NAND flash memory

    Publication Year: 2010 , Page(s): 46 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (567 KB) |  | HTML iconHTML  

    Self-aligned shallow trench isolation recess effect on 42 nm node NAND flash to achieve high performance and good reliability has been studied and demonstrated. As cell STI recess is increased by 23 nm, 29% narrower cell Vth distribution width and 54% less cell Vth shift after 125°C, 2 hours can be obtained. Furthermore, the endurance window is obviously improved ~0.5V as the distance of the active area edge to control gate (CG) is increased at the same time. Deeper STI recess and enough active area edge to CG distance are a promising profile for floating gate based NAND flash at 42 nm node and beyond. View full abstract»

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  • Gate stack etch induced reliability issues in nitrided-based trapping storage cells

    Publication Year: 2010 , Page(s): 48 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (399 KB) |  | HTML iconHTML  

    Gate stack etch profile-induced reliability issues are reviewed and discussed. A taper nitride profile, which blocks source/drain (S/D) implantation, induces an unwanted n- region. In other words, residual charges above the junctions can deplete the n- much easily and cut off the channel formation. This will cause poor string resistance distribution, worse endurance behavior, program and erase (P/E) speed degradation, and sub-threshold swing (SS) degradation in nitride trap NAND flash memories. Improvements are achieved once gate stacks are etched more vertical. In addition, the behavior of program disturbance is also affected. Depleted S/D junctions result in high potential difference between channel and junctions at disturbed cells. Such high lateral field will induce junction breakdown and excess electrons will be accelerated and injected into the nitride layer. View full abstract»

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  • Tunnel oxide degradation in TANOS devices and its origin

    Publication Year: 2010 , Page(s): 50 - 51
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB) |  | HTML iconHTML  

    Tunnel oxide degradation in TANOS devices and its origins were investigated in terms of program, erase, and endurance device operation modes. It was found that the erase operation may cause significant tunnel oxide degradation, while the degradation due to program operation is negligible. In the erase and endurance modes, tunnel oxide degradation is primarily controlled by the process of electron ejection from the SiN trapping layer to the substrate. View full abstract»

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  • Investigation of trapping/detrapping mechanisms in Al2O3 electron/hole traps and their influence on TANOS memory operations

    Publication Year: 2010 , Page(s): 52 - 53
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (511 KB) |  | HTML iconHTML  

    Alumina is a key material for developing innovative Charge-Trapping Non-Volatile Memory (CT-NVM) devices. Al2O3 is used to implement the top dielectric in TANOS devices, and it has been proposed as trapping layer and to engineer the tunnel dielectric. Despite the large use of this material, the quantitative investigation of defect features still lacks. In this scenario, the purpose of this work is to investigate the physics of electron/hole trapping/detrapping mechanisms in Al2O3. Combining I-V and C-V measurements with a physical model we derive the energy levels of electron/hole traps and the location of electron/hole charge. The influence of electron/hole alumina traps on TANOS operations and reliability is investigated. View full abstract»

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  • Hybrid silicon nanocrystals/SiN charge trapping layer with high-k dielectrics for FN and CHE programming

    Publication Year: 2010 , Page(s): 54 - 55
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2788 KB) |  | HTML iconHTML  

    Silicon nanocrystal (Si-nc) trapping layers offer several advantages on standard poly-Si floating gates, as improved data retention after endurance in particular at high temperatures, robustness toward oxide defects, two-bits per cell storage and full compatibility toward CMOS process. It has also been shown that coupling the Si-nc concept with high-k control dielectrics, by improving the gate coupling ratio, enables Fowler-Nordheim (FN) program/erase. However, one of the key limitations of Si-nc memories is the limited memory window which is not suitable for multi-level memory applications. The use of two stacked Si-ncs layers to increase the number of trapping sites has been previously discussed in the literature with a SiO2 control oxide. In this work, we present memory devices with double stacked Si-nc layers and high-k (HfAlO-based) control dielectrics. We also propose to cover the 2nd Si-nc layer with a thin nitride layer (leading to an hybrid Si-nc / SiN memory structure) in order to boost further the memory characteristics. We will show that these devices offer improved memory programming window both in FN regime and in channel hot electron injection (CHE), which makes them compatible with NAND and NOR applications. Finally, a model involving valence band electrons from the top Si-ncs layer is proposed to explain the electrical results. View full abstract»

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  • Layered HfSiON-based tunnel stacks for voltage reduction and improved reliability in TANOS memories

    Publication Year: 2010 , Page(s): 56 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (791 KB) |  | HTML iconHTML  

    In this work we present the integration of Band Engineered TANOS-like memories using HfSiON in the tunnel stack to boost the programming efficiency and improve cycling. An accurate correlation analysis between the gate-stack material physical properties and the memory performances is presented. In particular, the importance of the nitridation step of HfSiON on the memory retention characteristics at high temperature is suggested. View full abstract»

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  • Current status of EUV lithography development in Japan

    Publication Year: 2010 , Page(s): 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (585 KB) |  | HTML iconHTML  

    Extreme Ultraviolet Lithography (EUVL) is a promising candidate for the device fabrication at feature sizes of a half pitch of 32 nm and below. An EUV lithography system (Fig. 1) is composed of various subsystems, such as the source, the optics, the exposure system, a mask, and the resist. Currently various consortia, private companies, universities, and research institutes are working on the development of EUV lithography in Japan. EUVA and Selete are involved in an EUVL-related NEDO project under MIRAI Scheme. The recent activities of those projects are described in this presentation. View full abstract»

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  • Evaluations for a highly scalable, reliable vertical channel SONOS memory

    Publication Year: 2010 , Page(s): 59 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (421 KB) |  | HTML iconHTML  

    A vertical channel SONOS memory, which is compatible with current CMOS process and has four physical storage nodes per unit area, is fabricated and electrically evaluated. Comparing with a planar device, the array cell tuning is much easier since the channel length is no longer limited by array area. After reviewing key performances including program/erase (P/E) speeds, second bit effect, program disturbance, endurance, and retention on a NOR-type array, it is found that four physical bits/cell is hard to achieve due to a serious program disturb. Unavoidable high energy 2nd hot electron between neighbor cells is identified as the root cause. In this paper, operation procedures and array layouts, which are suitable for three physical bits per cell (3bits/cell), is then proposed. View full abstract»

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