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Reliability Physics Symposium (IRPS), 2010 IEEE International

Date 2-6 May 2010

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Displaying Results 1 - 25 of 209
  • [Copyright notice]

    Publication Year: 2010 , Page(s): 1
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  • Preface

    Publication Year: 2010 , Page(s): 1
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  • A review on the reliability of GaN-based laser diodes

    Publication Year: 2010 , Page(s): 1 - 6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    University of Padova in collaboration with Panasonic Corp. has developed in the recent years an in depth reliability analysis of Blu-Ray InGaN Laser Diodes (LD) submitted to CW stress at different driving conditions. The reliability analysis has been focused towards a) the identification of the effects of current, temperature and optical field and b) the identification of the physical mechanism related to degradation. Results show that LD devices exhibit a gradual threshold current increase, while slope efficiency is almost not affected by the ageing treatment. Degradation rate is found to depend on stress temperature and on current level, while it does not significantly depend on the optical field in the cavity. Within this paper we demonstrate that: (i) the degradation rate shows a linear correlation with stress current level; (ii) the Ith increase is correlated to the decrease in non-radiative lifetime (τnr); (iii) stress temperature acts as an accelerating factor for LD degradation; (iv) pure thermal storage does not significantly degrade LDs characteristics. View full abstract»

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  • Using a Smart Grid to evolve a reliable power system

    Publication Year: 2010 , Page(s): 1 - 2
    Cited by:  Papers (1)
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  • Announcement

    Publication Year: 2010 , Page(s): 1
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  • Committees

    Publication Year: 2010 , Page(s): 1 - 5
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  • Awards

    Publication Year: 2010 , Page(s): 1 - 4
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  • Tutorial program

    Publication Year: 2010 , Page(s): 1 - 6
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  • Biographies

    Publication Year: 2010 , Page(s): 1 - 59
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  • Table of contents

    Publication Year: 2010 , Page(s): 1 - 14
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  • The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress

    Publication Year: 2010 , Page(s): 7 - 15
    Cited by:  Papers (66)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (575 KB) |  | HTML iconHTML  

    The physical origin of the Negative Bias Temperature Instability (NBTI) is still under debate. In this work we analyze the single defects constituting NBTI. We introduce a new measurement technique stimulating a charging of these defects. By employing a statistical analysis of many stochastic stimulation processes of the same defect we are able to determine the electric field and the temperature dependence of these defects with great precision. Based on our experiments we present and verify a new, physics-based, quantitative model allowing a precise prediction of NBTI degradation and recovery. This model takes the stress history into account and also provides a prediction for degradation due to AC-NBTI and an understanding of the special features seen in conjunction with AC-NBTI. View full abstract»

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  • The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability

    Publication Year: 2010 , Page(s): 16 - 25
    Cited by:  Papers (79)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    We introduce a new method to analyze the statistical properties of the defects responsible for the ubiquitous recovery behavior following negative bias temperature stress, which we term time dependent defect spectroscopy (TDDS). The TDDS relies on small-area metal-oxide-semiconductor field effect transistors (MOSFETs) where recovery proceeds in discrete steps. Contrary to techniques for the analysis of random telegraph noise (RTN), which only allow to monitor the defect behavior in a rather narrow window, the TDDS can be used to study the capture and emission times of the defects over an extremely wide range. We demonstrate that the recoverable component of NBTI is due to thermally activated hole capture and emission in individual defects with a very wide distribution of time constants, consistent with nonradiative multiphonon theory previously applied to the analysis of RTN. The defects responsible for this process show a number of peculiar features similar to anomalous RTN previously observed in nMOS transistors. A quantitative model is suggested which can explain the bias as well as the temperature dependence of the characteristic time constants. Furthermore, it is shown how the new model naturally explains the various abnormalities observed. View full abstract»

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  • Origin of NBTI variability in deeply scaled pFETs

    Publication Year: 2010 , Page(s): 26 - 32
    Cited by:  Papers (76)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (631 KB) |  | HTML iconHTML  

    The similarity between Random Telegraph Noise and Negative Bias Temperature Instability (NBTI) relaxation is further demonstrated by the observation of exponentially-distributed threshold voltage shifts corresponding to single-carrier discharges in NBTI transients in deeply scaled pFETs. A SPICE-based simplified channel percolation model is devised to confirm this behavior. The overall device-to-device ΔVth distribution following NBTI stress is argued to be a convolution of exponential distributions of uncorrelated individual charged defects Poisson-distributed in number. An analytical description of the total NBTI threshold voltage shift distribution is derived, allowing, among other things, linking its first two moments with the average number of defects per device. View full abstract»

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  • Two independent components modeling for Negative Bias Temperature Instability

    Publication Year: 2010 , Page(s): 33 - 42
    Cited by:  Papers (56)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (785 KB) |  | HTML iconHTML  

    Based on vast experimental dataset obtained from different technologies (pure or nitrided SiO2 and HK), we suggest that Negative Bias Temperature Instability is made of two independent components, presenting different voltage and temperature acceleration factors as well as process dependences. The recoverable part, subject to fast transient effects, is shown to obey field-assisted LRME hole trapping/detrapping processes. The permanent part is shown to be made of an equal number of interface traps and positive fixed charges, as resulting from hydrogen transfer to oxygen bridge. This hydrogen transfer was shown for the first time to be reversible allowing in-depth analysis of the microscopic mechanisms at play. View full abstract»

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  • Recovery-free electron spin resonance observations of NBTI degradation

    Publication Year: 2010 , Page(s): 43 - 49
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (717 KB) |  | HTML iconHTML  

    We have developed an approach to perform “on the fly” electron spin resonance (OTF-ESR) measurements of negative bias temperature instability (NBTI) defect generation. This OTF-ESR approach allows for an atomic-scale identification of the defects involved in NBTI free of any recovery contamination. We demonstrate that, during NBTI stressing at elevated temperature and modest negative oxide bias, positively charged oxygen vacancy sites (E' centers) are generated. Upon removal of the NBTI stressing conditions, the E' center density quickly recovers to that of its pre-stress values. When similar measurements are made with zero oxide bias at elevated temperature or negative oxide bias at room temperature, the E' defect density does not change. These observations strongly indicate that NBTI is triggered by inversion layer hole capture at an E' precursor site which then leads to the depassivation of nearby interface states. View full abstract»

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  • PBTI relaxation dynamics after AC vs. DC stress in high-k/metal gate stacks

    Publication Year: 2010 , Page(s): 50 - 54
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (573 KB) |  | HTML iconHTML  

    A detailed study on PBTI relaxation after AC and DC stress in high-k nFETs is reported. First, Vt shift during AC and DC stress are examined, showing that the PBTI time evolution depends on the stress mode due to the relaxation effect. Then, comparison of relaxation after different stress types reveals large difference in the relaxation behavior at short times, whereas AC and DC relaxation are observed to merge at longer times. The “time-to-merge” rapidly increases with stress time and it strongly depends on the duty cycle. From a series of “Stress-Relax-Stress” measurement, we also demonstrate that the charge trapping and de-trapping process are highly correlated through “trap level”. A simple model from a trap distribution point of view is proposed to rationalize the above observations. These observations provide new insight into the trapping dynamics during PBTI. View full abstract»

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  • Off state incorporation into the 3 energy mode device lifetime modeling for advanced 40nm CMOS node

    Publication Year: 2010 , Page(s): 55 - 64
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (590 KB) |  | HTML iconHTML  

    Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been done on the distinct impact of the measuring bias and stressing conditions in Sub-VT regime. The latter can be much more degraded than On-state parameters showing the amphoteric nature of Si-H bonds breaking rates throughout the channel-GDO. Off-mode damage has been included in the 3 mode energy device lifetime giving a useful modeling for any AC waveforms suitable for digital to analog operations. View full abstract»

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  • Mobility enhancement due to charge trapping & defect generation: Physics of self-compensated BTI

    Publication Year: 2010 , Page(s): 65 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (571 KB) |  | HTML iconHTML  

    Threshold voltage VT of a transistor degrades with time both due to the formation of defects at the oxide/Si interface, as well as charge trapping into bulk defects - a phenomenon commonly known as Bias Temperature Instability (BTI). However, we have shown earlier that with appropriate mobility vs. vertical effective electric field characteristics, transistor's drivability (i.e., drain current) can be made far less sensitive to the NBTI-induced threshold voltage degradation ΔVT, than previously presumed. Higher steepness of the mobility-field characteristics results in an increase in mobility due to interface defects, which can self-compensate the effect of ΔVT on drain current. In this paper, for the first time we analyze the additional effect of PBTI-induced ΔVT in NMOS transistor parameters and show that mobility at constant gate voltage always increases with PBTI, irrespective of the mobility-field steepness. Therefore, self-compensation for PBTI is even more pronounced compared to NBTI. Next, we demonstrate the consequence of self-compensation via an intuitive analysis in simple digital circuits and show that lifetime of digital ICs increases dramatically once we incorporate the effect of self-compensation by using appropriate sign for mobility variation at constant gate voltage. This might in turn reduce the requirement of different circuit level optimization techniques, currently employed to manage transistor variabilities. Finally, we establish the importance of flatter transfer characteristics for self-compensation, which can be obtained through advanced CMOS technologies. View full abstract»

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  • Understanding noise measurements in MOSFETs: the role of traps structural relaxation

    Publication Year: 2010 , Page(s): 73 - 79
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (434 KB) |  | HTML iconHTML  

    The presented theoretical analysis of random telegraph signal (RTS) and 1/f noise data provides consistent interpretation of the measurement results allowing trap characteristics to be extracted and the atomic structure of oxide traps to be identified. We emphasize the critical role of the lattice structural relaxation associated with charge trapping/detrapping, which represents one of the major factors controlling electron capture/emission times. View full abstract»

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  • Reliability study of bilayer graphene - material for future transistor and interconnect

    Publication Year: 2010 , Page(s): 80 - 83
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (494 KB) |  | HTML iconHTML  

    Graphene is considered to be promising candidate for future transistor and interconnects material in integrated circuits because of its high intrinsic mobility and current-carrying capacity outperforming Cu. Particularly, bilayer graphene (BLG) systems offer controllable and wide band gap tunability without the need for nontrivial atomically precise nanoribbon patterning, which is indispensable to band gap engineering of monolayer graphene. Hence, novel devices consisting of BLG as both transistors and interconnects in combination with well-established Cu interconnects is conceivable. In this frame, this study has aimed to address reliability limiting factors of BLG/Cu contacts and current-carrying capacity. View full abstract»

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  • Failure analysis of resistive switching devices

    Publication Year: 2010 , Page(s): 84 - 88
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    Cycling failures for resistive switching devices are discussed based on array statistics measured on Cu2O metal-insulator-metal (MIM) devices. Four types of failures can be identified under rigorous testing conditions. The rate of these failures can be reduced by optimizing operation methods, which has significant impact on cycling endurance and yield. Failures related to data loss may have their origin in material stability. View full abstract»

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  • Charging and discharging characteristics of metal nanocrystals in degraded dielectric stacks

    Publication Year: 2010 , Page(s): 89 - 93
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (927 KB) |  | HTML iconHTML  

    The conduction mechanisms of dielectric breakdown (BD) in MOS capacitor structure with nanocrystals (NCs) embedded in bi-layer gate stacks (SiO2/Al2O3) are studied systematically. Using a unique stressing methodology of inducing a BD path in one dielectric layer, the charging and discharging phenomenon of the metal NCs and leakage mechanism in the degraded gate stacks are found to be strongly dependent on the lateral charge tunneling/hopping among the NCs. It is found that the localized BD not only affects charge holding capability of the affected NCs, but also provides a leakage path for the charges stored in the surrounding NCs. Thus, the discharging of NCs via the BD path is not a localized phenomenon. View full abstract»

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  • Characterization of Gate-All-Around Si-NWFET, including Rsd, cylindrical coordinate based 1/f noise and hot carrier effects

    Publication Year: 2010 , Page(s): 94 - 98
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB) |  | HTML iconHTML  

    In this paper, we introduce the cylindrical coordinate based flicker noise model for Silicon NanoWire Field Effect Transistor (Si-NWFET) with Gate-All-Around (GAA) structure. For the accurate extraction of the volume trap density, Nt, with 1/f noise modeling, the parameters which represent the intrinsic channel properties are determined by rejecting the series resistance Rsd effect. Due to the random distribution of traps in Si-NWFETs, the 1/f noise data are obtained by averaging the drain current power spectral density, Sid, for several devices. By using the proposed 1/f model, the extracted volume trap density is compared for three different oxide processes (ISSG/RTO/GNOx) and verified by hot carrier stress test. View full abstract»

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  • Thermal disturbance and its impact on reliability of phase-change memory studied by the micro-thermal stage

    Publication Year: 2010 , Page(s): 99 - 103
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (366 KB) |  | HTML iconHTML  

    In this paper, we study thermal disturbance and its impact on reliability using a novel measurement structure - the micro-thermal stage (MTS). The small thermal time constant of the MTS extends the time-scale of temperature dependence measurement to ~100 μs. The reliability of phase-change memory (PCM) is evaluated in terms of data retention and variation of the high resistance (RESET) state resistance (RRESET) and the threshold switching voltage (Vth). We experimentally show how the impact of thermal disturbances on retention is accumulated and its dependence on the electric field. The thermal disturbance effect on RRRESET variation changes with time and it is the largest for the shortest time delay after RESET programming. Thermal disturbance can cause at least 25 and 100% variation for RRRESET and Vth respectively in the given thermal disturbance scenario. We propose an effective method to exploit thermal disturbance to make multi-bit operation more robust. View full abstract»

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  • Mature processability and manufacturability by characterizing VT and Vmin behaviors induced by NBTI and AHTOL test

    Publication Year: 2010 , Page(s): 104 - 110
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (813 KB) |  | HTML iconHTML  

    A systematical reliability assessment for technology process that is essential for technology feasibility and qualification is presented by addressing physical and electrical characterization and reliability evaluation. By varying the duty cycle of enhanced pulsed radio frequency (eprf) technique used for the gate oxynitridation, the effects of nitrogen concentration and profile at SiO2/Si interface on VT and Vmin shift of thin oxide pMOSFET (~20A) and SRAM, which result from negative bias temperature stability (NBTI) and accelerated high temperature operating life (AHTOL) stress test, are meticulously investigated. Using secondary ion mass spectrometry (SIMS) and high resolution Rutherford back scattering (H-RBS), nitrogen concentration and profile at the interface are carefully characterized. It is found that pMOSFET device processed with 10% of eprf provides ~2× longer NBTI lifetimes than with 20% of eprf due to lower nitrogen concentration at the interface. Furthermore, Vmin shift of SRAM with 10% of eprf, which is caused by AHTOL test conditioned at 140°C with 1.4× Vdd, is ~3~4× less than with 20% of eprf. In fact, a nano-probing technique elucidates that Vmin shift is mainly attributed to the mismatch of VT between pull-up (PU) transistors in SRAM induced by NBTI stemmed from AHTOL test. It is also empirically shown that Vmin shift behavior is in good agreement with the read margin rather than the write. Accordingly, a stabilized Vmin drift behavior consistently adheres to the write margin. Hence, the optimization of interfacial nitrogen concentration results in less pMOSFET NBTI degradation so as to efficiently suppress Vmin shift of SRAM. Besides, increasing PU transistor size that decreases the γ value (the ratio of Ion current of PG to PU) can also reduce Vmin shift during AHTOL test. Finally, matu- - re processability and manufacturability are attained by characterizing VT and Vmin behaviors for pMOSFET and SRAM from the front-end-of-line (FEOL) process optimization and SRAM bit-cell design aspect. View full abstract»

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