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Signal Propagation on Interconnects (SPI), 2010 IEEE 14th Workshop on

Date 9-12 May 2010

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Displaying Results 1 - 25 of 69
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • [Front matter]

    Publication Year: 2010, Page(s):1 - 3
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • Committee

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • Table of contents

    Publication Year: 2010, Page(s):1 - 4
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  • [Blank page]

    Publication Year: 2010, Page(s):1 - 2
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  • Session I: Interconnect modeling and system design issues

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • Response variability of high-speed interconnects via Hermite Polynomial Chaos

    Publication Year: 2010, Page(s):3 - 6
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (747 KB) | HTML iconHTML

    This paper focuses on the stochastic analysis of dynamical circuits via the Hermite Polynomial Chaos theory. The proposed approach facilitates the inclusion of external uncertainties, like tolerances or process variations, in the circuit analysis. The mechanics of the method amounts to expanding the output variables into a sum of a limited number of orthogonal basis functions and generating an ext... View full abstract»

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  • Network modeling of vertical signal interconnections in parallel reference plane structures on printed circuit boards

    Publication Year: 2010, Page(s):7 - 8
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (95 KB) | HTML iconHTML

    Signal path transitions through parallel reference plane structures on printed-circuit boards are investigated. The analysis is based on an equivalent circuit including the interconnect inductances, the signal source and load impedance. All required network elements can be calculated by simple formulas, including simple closed-form expressions for the self and mutual inductances in the central boa... View full abstract»

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  • Benefit on interconnect performance of a relaxed wire density in a 45 nm node of the Back End of Line

    Publication Year: 2010, Page(s):9 - 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (155 KB) | HTML iconHTML

    High speed digital ICs require short delay between successive gates and minimum crosstalk levels between adjacent interconnects. But crosstalk and delay performance are degraded with interconnect length. So designers can use large drivers with fast response to compensate global falloff due to long interconnects with critical delay and crosstalk levels. They must also trade off IC's cost and consum... View full abstract»

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  • Session II: Power integrity

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • Modeling of chip-package resonance in power distribution networks by an impulse response

    Publication Year: 2010, Page(s):15 - 18
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1700 KB) | HTML iconHTML

    This paper proposes a method for modeling chip-package resonance using impulse response. To extract chip and package electrical circuit parameters, we assume a circuit equivalent to the loop from the chip to the package decoupling capacitor as the RL-RC parallel circuit and convert it into an RLC parallel circuit. We apply this method to devise an electrical circuit model capable of expressing chi... View full abstract»

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  • Measurement of on-chip I/O power supply noise and correlation verification between noise magnitude and delay increase due to SSO

    Publication Year: 2010, Page(s):19 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (631 KB) | HTML iconHTML

    This paper presents measurement results of on-chip noise on power and ground rings for I/O (input/output) cells in a simple test structure fabricated in 90nm process. We also show measured timings of an output signal from chip to PCB board, and examine the relation between the magnitude of I/O power supply noise and the output transition timings. View full abstract»

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  • TSV-aware IDF-based power prediction for FPGA

    Publication Year: 2010, Page(s):21 - 24
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB) | HTML iconHTML

    In this paper, we present a new power prediction method with application in regular structures such as FPGAs. We will mainly discuss the effects of through-silicon-via (TSV) and interconnects in order to offer a robust IDF-based solution for power prediction problem. In our survey, we will show that TSV increases the average wire-length by up to 16 percent that in turn leads to 16 percent elevatio... View full abstract»

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  • Session III: Frequency domain simulation

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • Effect of mixed-reference planes on single-ended and differential links in multilayer substrates

    Publication Year: 2010, Page(s):27 - 30
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (525 KB) | HTML iconHTML

    In this paper, efficient physics-based models are used to examine diverse differential and single-ended link configurations on multilayer substrates with mixed reference planes (i.e. links running between ground and power planes). The effect of different plane assignments is studied and the results are validated with a general purpose full-wave solver. It is shown that the plane configuration affe... View full abstract»

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  • Impact by an orthogonal metal grid upon differential- and common-mode characteristics of coupled lines in PCB technology structures

    Publication Year: 2010, Page(s):31 - 34
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1406 KB) | HTML iconHTML

    This paper deals with a rigorous study of the impact by perpendicular metal grids on the characteristics of microstrip and coplanar coupled transmission lines. An electromagnetic analysis shows the variations of the propagation parameters in common and differential modes for each type of lines, in the presence of a metal grid. As transmission zeroes are liable to occur at certain frequencies, in p... View full abstract»

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  • Characterization and modeling of RF substrate coupling effects due to vertical interconnects in 3D integrated circuit stacking

    Publication Year: 2010, Page(s):35 - 38
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2244 KB) | HTML iconHTML

    This paper discusses substrate coupling effects in 3D integrated circuits carried by TSV interconnects (Through Silicon Vias). These electrical couplings lead to several impacts on 3D circuit performance. RF (Radio Frequency) characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling and make obvious this phenomenon. New modeling ... View full abstract»

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  • Session IV: Parameter extraction

    Publication Year: 2010, Page(s): 1
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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