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Field-Programmable Custom Computing Machines (FCCM), 2010 18th IEEE Annual International Symposium on

Date 2-4 May 2010

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Displaying Results 1 - 25 of 55
  • [Front cover]

    Publication Year: 2010 , Page(s): C1
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  • [Title page i]

    Publication Year: 2010 , Page(s): i
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  • [Title page iii]

    Publication Year: 2010 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2010 , Page(s): iv
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  • Table of contents

    Publication Year: 2010 , Page(s): v - viii
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  • Message from the General Chairs

    Publication Year: 2010 , Page(s): ix
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  • Message from the Program Chairs

    Publication Year: 2010 , Page(s): x
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  • Organization

    Publication Year: 2010 , Page(s): xi
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  • Steering Committee

    Publication Year: 2010 , Page(s): xii
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  • Program Committee

    Publication Year: 2010 , Page(s): xiii - xiv
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  • Additional reviewers

    Publication Year: 2010 , Page(s): xv - xvi
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  • Fast and Efficient FPGA-Based Feature Detection Employing the SURF Algorithm

    Publication Year: 2010 , Page(s): 3 - 10
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (463 KB) |  | HTML iconHTML  

    Feature detectors are schemes that locate and describe points or regions of `interest' in an image. Today there are numerous machine vision applications needing efficient feature detectors that can work on Real-time; moreover, since this detection is one of the most time consuming tasks in several vision devices, the speed of the feature detection schemes severally affects the effectiveness of the... View full abstract»

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  • Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs

    Publication Year: 2010 , Page(s): 11 - 18
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (413 KB) |  | HTML iconHTML  

    Face detection is an important aspect for biometrics, video surveillance and human computer interaction. We present a multi-GPU implementation of the Viola-Jones face detection algorithm that meets the performance of the fastest known FPGA implementation. The GPU design offers far lower development costs, but the FPGA implementation consumes less power. We discuss the performance programming requi... View full abstract»

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  • Accelerating the Nonuniform Fast Fourier Transform Using FPGAs

    Publication Year: 2010 , Page(s): 19 - 26
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1166 KB) |  | HTML iconHTML  

    We present an FPGA accelerator for the Non-uniform Fast Fourier Transform, which is a technique to reconstruct images from arbitrarily sampled data. We accelerate the compute-intensive interpolation step of the NuFFT Gridding algorithm by implementing it on an FPGA. In order to ensure efficient memory performance, we present a novel FPGA implementation for Geometric Tiling based sorting of the arb... View full abstract»

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  • Increased Performace of FPGA-Based Color Classification System

    Publication Year: 2010 , Page(s): 29 - 32
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (452 KB) |  | HTML iconHTML  

    This paper presents a hardware architecture for increased performance of color classification. In our architecture, color classification, based on an AdaBoost algorithm, identifies a pixel as having the color of interest or not. We designed the proposed architecture using Verilog HDL and implemented the design in a Xilinx Virtex-5 FPGA. The architecture for color classification can have 598 times ... View full abstract»

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  • Pipelined Hardware Architecture for High-Speed Optical Flow Estimation Using FPGA

    Publication Year: 2010 , Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (731 KB) |  | HTML iconHTML  

    Optical flow is a motion field estimation method that has a wide range of applications. In this paper, we present a fully pipelined hardware architecture for high-speed optical flow estimation based on a full-search block matching algorithm. A census transform is applied to the corresponding pixels in the current and previous frame. The similarity between two census vectors within the search area ... View full abstract»

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  • Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive

    Publication Year: 2010 , Page(s): 39 - 46
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (682 KB) |  | HTML iconHTML  

    As chips have moved from homogeneous single core systems to much more complex, heterogeneous multi-core systems, the ability to create both uniform and efficient operating system services has begun to diminish. The importance of these services suggests that these primitives should no longer be virtual, but rather physical services built into modern computing devices. In this paper we outline some ... View full abstract»

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  • Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration

    Publication Year: 2010 , Page(s): 47 - 54
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU), which is induced by radiation effect. This paper presents a technique for ensuring reliable softcore processor implementation on SRAM-based FPGAs. Although an FPGA is susceptible to SEUs, these faults can be corrected as a result of its reconfigurability. We propose techniques for SEU mitigation and rec... View full abstract»

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  • Energy-Aware Optimisation for Run-Time Reconfiguration

    Publication Year: 2010 , Page(s): 55 - 62
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (316 KB) |  | HTML iconHTML  

    Run-time reconfiguration has been shown to produce power and energy efficient designs. However, it is important to take into account the energy overhead of the reconfiguration process itself. This paper presents an analytical model that covers the effects of power consumption and configuration speed of the reconfiguration process. Based on this model, a method is introduced that establishes the op... View full abstract»

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  • A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems

    Publication Year: 2010 , Page(s): 65 - 68
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (446 KB) |  | HTML iconHTML  

    In this paper, we propose an efficient online task scheduling algorithm which targets 2D FPGA area partitioning model and takes into account the data dependency and the data communications 1) among hardware tasks and 2) between hardware tasks and external devices which have not been explicitly investigated in previous work. In the experiment with 10000 workloads, the evaluation result shows that o... View full abstract»

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  • Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

    Publication Year: 2010 , Page(s): 69 - 72
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    The architecture of Xilinx FPGAs, has changed remarkable with respect to their ability to implement runtime reconfigurable systems throughout the last generations. This paper will discuss these changes and reveal an on-FPGA communication architecture that is especially tailored to Xilinx Virtex-5 FPGAs. With this architecture, modules can be integrated in a two-dimensional grid with more than a hu... View full abstract»

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  • Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-Based FPGAs

    Publication Year: 2010 , Page(s): 73 - 76
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    SRAM-based FPGAs are susceptible to Single-Event Upsets (SEUs) in radiation-exposed environments due to their configuration memory. We propose a new scheme for the diagnosis and recovery from upsets that combines i) duplication of the core to be protected, ii) partial reconfiguration to reconfigure the faulty part only, and iii) hardcore processor(s) for deciding when and which part will be reconf... View full abstract»

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  • Hardware Acceleration of Approximate Tandem Repeat Detection

    Publication Year: 2010 , Page(s): 79 - 86
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (281 KB) |  | HTML iconHTML  

    Understanding the structure and function of DNA sequences represents an important area of research in modern biology. Unfortunately, analysis of such data is often complicated by the presence of mutations introduced by evolutionary processes. At the lowest scale, these usually occur in biological sequences as character substitutions, insertions or deletions (indel). They increase the time-complexi... View full abstract»

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  • Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence

    Publication Year: 2010 , Page(s): 87 - 94
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (410 KB) |  | HTML iconHTML  

    RNA folding is a compute-intensive task that lies at the core of search applications in bioinformatics such as RNAfold and UNAFold. In this work, we analyze the Zuker RNA folding algorithm, which is challenging to accelerate because it is resource intensive and has a large number of variable-length dependencies. We use a technique of Lyngso to rewrite the recurrence in a form that makes polyhedral... View full abstract»

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  • Reaping the Processing Potential of FPGA on Double-Precision Floating-Point Operations: An Eigenvalue Solver Case Study

    Publication Year: 2010 , Page(s): 95 - 102
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    Many scientific applications such as electromagnetics require their operations carried out in double-precision floating-point format. The efficiency of these applications is mainly subject to the floating-point processing performance on the target processors. In this work, we use an eigenvalue solver application as a case study to demonstrate the processing potential of an FPGA device when dealing... View full abstract»

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