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Solid-State Circuits Conference, 1996. ESSCIRC '96. Proceedings of the 22nd European

Date 17-19 Sept. 1996

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Displaying Results 1 - 25 of 115
  • [Front cover]

    Publication Year: 1996 , Page(s): 1
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  • Proceedings of the 22nd European Solid-State Circuits Conference

    Publication Year: 1996 , Page(s): I
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  • Copyright page

    Publication Year: 1996 , Page(s): II
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  • Foreword

    Publication Year: 1996 , Page(s): III
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  • Conference Organization

    Publication Year: 1996 , Page(s): IV
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  • Program Committee

    Publication Year: 1996 , Page(s): IV
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  • Corresponding Members

    Publication Year: 1996 , Page(s): IV
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  • Table of contents

    Publication Year: 1996 , Page(s): V - IX
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  • Invited papers

    Publication Year: 1996 , Page(s): 1
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  • IC Requirements for Multimedia TV

    Publication Year: 1996 , Page(s): 2 - 9
    Cited by:  Patents (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1841 KB)  

    This paper describes the key technologies and trends for multimedia applications. The common use of digital processing has opened the door for new applications and new markets, from consumer products to communications and computing products. It also significantly re-invents traditional products from TVs to computers. Integrated Circuits and IC technologies have been the prerequisite for these mult... View full abstract»

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  • Analog VLSI Computations

    Publication Year: 1996 , Page(s): 10
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (18 KB)  

    First Page of the Article
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  • RF Integrated Circuits in Standard CMOS Technologies

    Publication Year: 1996 , Page(s): 11 - 18
    Cited by:  Papers (2)  |  Patents (18)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (3163 KB)  

    Since several years the research in the possibilities of CMOS technologies for RF applications is growning enormously. The trend towards deep sub-micron technologies allows the operation frequency of CMOS circuits above 1GHz, which opens the way to integrated CMOS RF circuits. Several research groups have developed high performance down-converters, low phase noise voltage controlled oscillators an... View full abstract»

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  • Integrated Smart Power Circuits Technology, Design and Application

    Publication Year: 1996 , Page(s): 19 - 26
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (2380 KB)  

    Integrated smart power circuits gain more and more importance, as many segments of microelectronics move towards system integration. The combination of many functions - analog, digital and power - on a single chip enable the design and production of even more miniaturized systems for different applications in the fields of automotive, industrial, telecommunication and electronic data processing. T... View full abstract»

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  • The Design of a High Performance Low Power Microprocessor

    Publication Year: 1996 , Page(s): 27 - 34
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (794 KB)  

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  • Future Directions in Mobile Communications

    Publication Year: 1996 , Page(s): 35 - 39
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (2356 KB)  

    This paper will outline the technological challenges faced in mobile telephones as wireless networks evolve further, to offer a multitude of services, including broadband services. View full abstract»

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  • Compact Modelling of Submicron CMOS

    Publication Year: 1996 , Page(s): 40 - 46
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (878 KB)  

    The accuracy of present-day compact MOS models and relevant benchmark criteria are reviewed. The impact on compact modelling of new CMOS applications and the rapid progress in process technology towards dimensions of 0.1 micron, will be discussed. View full abstract»

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  • Contributions

    Publication Year: 1996 , Page(s): 47
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  • A 150MHz 5.4mW Track&Hold operated at 3V supply

    Publication Year: 1996 , Page(s): 48 - 51
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1134 KB)  

    A fully-differential closed-loop Track&Hold circuit is proposed. It has been realized in a 0.7¿m BiCMOS technology. The circuit achieves more than 8bit linearity with sampling frequency up to 150MHz. It operates from a single 3V supply voltage and dissipates 5.4mW power. View full abstract»

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  • A 50 MHz, standard CMOS, pulse equalizer for hard disk read channels

    Publication Year: 1996 , Page(s): 52 - 55
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1098 KB)  

    A pulse equalizer for hard disk systems is presented. Opposed to classical realizations it is full CMOS while operating at 50 MHz cut-off frequency. For pulse slimming, the equalizer is capable of 13 dB selective boost around the cut-off frequency. The equalizer is a gm-C, seventh order 0.05° equiripple-on-the-phase low pass filter. It is made out of highly symmetrical biquads with elementary OTA... View full abstract»

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  • 20-90 MHz Current-Controlled Sinusoidal Oscillator

    Publication Year: 1996 , Page(s): 56 - 59
    Cited by:  Papers (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (803 KB)  

    A current-controlled sinusoïdal oscillator based on the Wien bridge oscillator is presented. The circuit acts in current mode and uses a second generation current conveyor. Its oscillation frequency, which can be varied from 20 to 90 MHz is adjustable from the bias current of a floatting resistor. The circuit has been implemented from SGS THOMSON in a 2¿m BICMOS technology. Measurement results a... View full abstract»

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  • A 2.1 MHz Crystal Oscillator Time Base with a Current Consumption under 500 nA

    Publication Year: 1996 , Page(s): 60 - 63
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1493 KB)  

    A micro-power circuit is encapsulated with a 2.1 MHz ZT-cut quartz in a vacuum package. The oscillator core has 2 complementary active MOSFETS and amplitude stabilization. New coupling and biasing circuits, and dynamic frequency dividers allow to achieve ±2 ppm frequency stability down to 1.8 V with a current under 0.5 ¿A. View full abstract»

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  • A high speed 0.7μm CMOS PLL circuit for clock/data recovery in interconnection systems

    Publication Year: 1996 , Page(s): 64 - 67
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (485 KB)  

    In this paper a CMOS PLL circuit realised for clock and data recovery in interconnection systems is presented. The purpose of this clock recovery PLL is to generate a clock with frequency and phase locked to the input NRZ data, in order to sample them in the optimum point. The topology of the circuit is characterised by two loops, one for the phase lock, the second for a frequency aided acquisitio... View full abstract»

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  • 1 Gb/s clock recovery PLL in 0.5 μm CMOS

    Publication Year: 1996 , Page(s): 68 - 71
    Cited by:  Papers (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (946 KB)  

    A clock recovery PLL is described for serial NRZ data transmission. The VCO works at only half the data rate, which means for a 1 Gb/s data rate the VCO runs at 500 MHz. A specially designed phase comparator uses both the rising and falling clock edges to compare clock and data. The VCO can typically be tuned from 350 MHz to 890 Mhz and the PLL locks between 850 Mb/s and 1.3 Gb/s. The circuit cons... View full abstract»

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  • A Low-Power True Single Phase Clocked (TSPC) Full-Adder

    Publication Year: 1996 , Page(s): 72 - 75
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1054 KB)  

    A TSPC full-adder circuit containing only 6 clock transistors and thus consuming significantly less power than recently published full-adders has been designed and characterized by simulation. It is composed of 36 transistors and consumes 220 ¿W @100 MHz when connected to a 5 V power supply, using a 0.8 ¿m standard CMOS process technology. This considers all parasitic capacitances as well as the... View full abstract»

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  • MHITIC: 8-Channels, 1-ns, Multi-Hit Time-to-Digital Converter CMOS Integrated Circuit

    Publication Year: 1996 , Page(s): 76 - 79
    Cited by:  Papers (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (663 KB)  

    A CMOS 8-channel, 1 ns bin size, 23 bit dynamic range multi-hit time-to-digital converter is presented in this paper. A new architecture mixing two previous TDC realizations has been adopted. The chip stores up to 32 events per channel with a double-hit resolution of 16 ns. A prototype of about 120 mm2 has been integrated in a 1 ¿m process. Test results show that performance, in partic... View full abstract»

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