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Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European

Date 19-21 Sept. 1995

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  • [Front cover]

    Publication Year: 1995, Page(s): 1
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  • Twenty-first European Solid-State Circuits Conference

    Publication Year: 1995, Page(s): I
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  • Copyright page

    Publication Year: 1995, Page(s): II
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  • Foreword

    Publication Year: 1995, Page(s): III
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  • Organizing Committee

    Publication Year: 1995, Page(s): IV
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  • Programme Committee

    Publication Year: 1995, Page(s): IV
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  • Corresponding Members

    Publication Year: 1995, Page(s): IV
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  • Table of contents

    Publication Year: 1995, Page(s):V - XII
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  • Contributions

    Publication Year: 1995, Page(s): 1
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  • Growth in the Semiconductor Industry

    Publication Year: 1995, Page(s):2 - 9
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1379 KB)

    The Semiconductor Industry is not only the driver in the Electronics Industry, the world's largest and fastest growing industry, but is also important in its own because of its size (100 B$ today, 1,000,000 people directly involved). The growth in this industry is three-fold: By 1998, sales will grow from 100 B$ today to over 200 B$, complexity will exceed 10 M gates per IC, and the innovation rat... View full abstract»

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  • Microelectronic Engineering Techniques with Electromagnetic Compatibility

    Publication Year: 1995, Page(s):10 - 11
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (72 KB)

    The term EMC (Electromagnetic Compatibility) includes, as generally might be known, all actions intended to eliminate electromagnetic interference in electronic systems. Challenges faced in the microelectronic area include growing systems complexity, higher operating speed, denser design at all levels of integration (chip, printed circuit board, MCM and system). View full abstract»

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  • FPGA Technology: Past, Present and Future

    Publication Year: 1995, Page(s):12 - 15
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (498 KB)

    Since their introduction in 1985, Field Programmable Gate Arrays (FPGAs) have become a preferred medium for implementing digital logic designs. The increased popularity of FPGAs results from significantly increased capability of FPGAs. This paper discusses the progress of FPGA technology in three areas: manufacturing process, architecture and software; and forecasts FPGA capabilities in the future... View full abstract»

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  • The Evolution of Microprocessor Design in Response to Silicon Process Evolution

    Publication Year: 1995, Page(s):16 - 19
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (309 KB)

    The interaction between silicon process evolution and design methodology and CAD tools for microprocessor technology will be described since the first commercial microprocessors to the present time. View full abstract»

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  • High Reliability Circuits for Space Applications

    Publication Year: 1995, Page(s):20 - 23
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (723 KB)

    The aim of this contribution is to present and discuss a methodology for the Development/Design and the Reliability/Quality Assurance of advanced Application Specific Integrated Circuits for digital, analog and microwave space applications. Starting from the technical and managerial requirements of space projects, the presentation shows today's procedure to fly advanced microelectronics. Areas of ... View full abstract»

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  • The IC Face of Multimedia

    Publication Year: 1995, Page(s): 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (45 KB)

    First Page of the Article
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  • Analog VLSI Data Converters - The First 10 Years

    Publication Year: 1995, Page(s):25 - 29
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    Commercial analog integrated circuits crossed the VLSI threshold of 10,000 transistors back in 1984. Today's analog VLSI circuits routinely surpass the million transistor complexity level. This Moore's Law increase in integration, combined with the analog designer's tradition of cleverness, is responsible for most of the decade's performance improvement in state-of-the-art data converters. Moore's... View full abstract»

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  • Microsystems: A Challenge for IC Designers

    Publication Year: 1995, Page(s):30 - 33
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (565 KB)

    Micromachined mechanics, magnetics and optics allow in conjunction with microelectronics the development of various microsystems. Scaling, co-integration and introduction of arrays of sensors and actuators render the task of the designer difficult. Innovations are required at the building block and system level. View full abstract»

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  • On-Line and Off-Line Testing: From Digital to Analog, from Circuits to Boards

    Publication Year: 1995, Page(s):34 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (565 KB)

    The goal of this paper is to review the design of circuits and systems featuring testing capabilities. Those capabilities include self-checking properties necessary for on-line testing as well as BIST. The design of fail-safe reliable ASICs and boards is broadly addressed. The basic milestones over the last 25 years are reviewed and longterm perspectives are discussed. View full abstract»

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  • A -100 dB THD, 120 dB SNR programmable gain amplifier in a 3.3 V, 0.5 μm CMOS process

    Publication Year: 1995, Page(s):38 - 41
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1415 KB)

    A fully differential amplifier that operates from a 3.3V±¿¿10% power-supply and featuring a -100dB THD at 2Vpp output voltage was realized. Equivalent input noise in the 100Hz - 10kHz audio-band is IμVrms, leading to a 120dB SNR. This amplifier is used as the core of a programmable gain cell in the front-end part of a ΣΔ A/D converter. The good linearity performance... View full abstract»

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  • 150 MHz Preamplifier for Magneto-Resistive Heads

    Publication Year: 1995, Page(s):42 - 45
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (998 KB)

    This paper presents the read section of a 10-channel preamplifier for hard-disk-drive applications that use magneto-resistive-read/inductive-write heads. Ten dedicated low-noise amplifier stages use a current-bias current-sense architecture with grounded magneto-resistive (MR) heads. The amplifier also contains gain stages common to all heads, a high-frequency gain-boost, an MR bias current-DAC an... View full abstract»

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  • CMOS Low-Distortion High-Frequency Variable-Gain Amplifier

    Publication Year: 1995, Page(s):46 - 49
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (409 KB)

    This paper describes the principle and design of a CMOS variable-gain amplifier for high-frequency applications. The operation of the differential circuit is based on a linear voltage-to-current conversion by means of a digitally controlled conversion impedance. Experimental results of the circuit show total harmonic distortion figures better than ¿60 dB and a gain accuracy of 0.05 dB over the ¿... View full abstract»

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  • An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops

    Publication Year: 1995, Page(s):50 - 53
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (630 KB)

    This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process. The propos... View full abstract»

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  • A 10 ps Resolution 1.6 ns Tuning Range CMOS Delay Line for Clock Deskewing in Data Recovery Systems

    Publication Year: 1995, Page(s):54 - 57
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1182 KB)

    This paper describes the realization of a high resolution CMOS delay line topology. Using on-chip microstrip lines, it is possible to realize a resolution of 10 ps. Cascading 3 different delay lines gives a tuning range of more than 1.6 ns. The delay elements are digital code controlled which makes integration with the DSP in a CMOS process possible. The realized IC is designed for use in the desk... View full abstract»

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  • A MOS Switched Capacitor Ladder Filter in SIMOX Technology for High Temperature Applications up to 300°C

    Publication Year: 1995, Page(s):58 - 61
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1974 KB)

    This paper describes techniques and methods used to realize a seventh order switched capacitor low pass filter in SIMOX technology. The filter has bessel characteristic and a 3dB-bandwidth of 20Hz at a clock frequency of 100kHz. Special design of transistors and transmission gates results in drastically reduced leakage currents. The power supply voltage is 10V. The temperature range is extended up... View full abstract»

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  • A 622-Mbps CMOS Bit/Frame Synchronizer for High-Speed Backplane Data Communication

    Publication Year: 1995, Page(s):62 - 65
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (607 KB)

    A new bit/frame synchronizer with optimum clock extractor and elastic serial-to-parallel (S/P) converter is presented. The circuit selects the suitable clock from equally phased multiple clocks generated by a PLL. The elastic S/P converter not only expands the bits but also recovers the frame synchronization. By our compact circuit implementation, the total hardware amount is greatly reduced. The ... View full abstract»

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