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Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European

Date 19-21 Sept. 1995

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Displaying Results 1 - 25 of 124
  • [Front cover]

    Page(s): 1
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    Freely Available from IEEE
  • Twenty-first European Solid-State Circuits Conference

    Page(s): I
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  • Copyright page

    Page(s): II
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  • Foreword

    Page(s): III
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  • Organizing Committee

    Page(s): IV
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  • Programme Committee

    Page(s): IV
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  • Corresponding Members

    Page(s): IV
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  • Table of contents

    Page(s): V - XII
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  • Contributions

    Page(s): 1
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  • Growth in the Semiconductor Industry

    Page(s): 2 - 9
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1379 KB)  

    The Semiconductor Industry is not only the driver in the Electronics Industry, the world's largest and fastest growing industry, but is also important in its own because of its size (100 B$ today, 1,000,000 people directly involved). The growth in this industry is three-fold: By 1998, sales will grow from 100 B$ today to over 200 B$, complexity will exceed 10 M gates per IC, and the innovation rate will have to grow to over twice the level of today. Growth in sales, increased complexity and shorter time-to-market pose new challenges to the design community. Do we have an answer to this? View full abstract»

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  • Microelectronic Engineering Techniques with Electromagnetic Compatibility

    Page(s): 10 - 11
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    The term EMC (Electromagnetic Compatibility) includes, as generally might be known, all actions intended to eliminate electromagnetic interference in electronic systems. Challenges faced in the microelectronic area include growing systems complexity, higher operating speed, denser design at all levels of integration (chip, printed circuit board, MCM and system). View full abstract»

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  • FPGA Technology: Past, Present and Future

    Page(s): 12 - 15
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (498 KB)  

    Since their introduction in 1985, Field Programmable Gate Arrays (FPGAs) have become a preferred medium for implementing digital logic designs. The increased popularity of FPGAs results from significantly increased capability of FPGAs. This paper discusses the progress of FPGA technology in three areas: manufacturing process, architecture and software; and forecasts FPGA capabilities in the future. View full abstract»

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  • The Evolution of Microprocessor Design in Response to Silicon Process Evolution

    Page(s): 16 - 19
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    The interaction between silicon process evolution and design methodology and CAD tools for microprocessor technology will be described since the first commercial microprocessors to the present time. View full abstract»

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  • High Reliability Circuits for Space Applications

    Page(s): 20 - 23
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    The aim of this contribution is to present and discuss a methodology for the Development/Design and the Reliability/Quality Assurance of advanced Application Specific Integrated Circuits for digital, analog and microwave space applications. Starting from the technical and managerial requirements of space projects, the presentation shows today's procedure to fly advanced microelectronics. Areas of potential improvements or revisions are identified to reach an approach that would be more compatible with the fast technological and industrial evolutions in Space industry. Various activities of the Design/Developpement and Quality/Reliability Assurance are addressed and illustrated. Study cases are presented on reliability prediction, failure mode effects analyses, definition of safe operating conditions, process evaluation and parts selection. The presentation draws some conclusions about the technical and managerial trends. View full abstract»

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  • Analog VLSI Data Converters - The First 10 Years

    Page(s): 25 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB)  

    Commercial analog integrated circuits crossed the VLSI threshold of 10,000 transistors back in 1984. Today's analog VLSI circuits routinely surpass the million transistor complexity level. This Moore's Law increase in integration, combined with the analog designer's tradition of cleverness, is responsible for most of the decade's performance improvement in state-of-the-art data converters. Moore's Law applies to MOS technologies, and scaled MOS processes have their limitations. Low frequency noise of the scaled MOSFET is a minor irritation, as 1/f noise is always vulnerable to architectural attack. Curiously, the world's most accurate low frequency data converters have long been produced with some of solid-state electronics' worst low frequency devices. A greater concern is the ever-decreasing supply voltage for analog circuits, but increasing capacitor values and device speeds compensate for this loss. VLSI data converters continue to improve in the 5V era at their traditional 2dB/year rate. Reduced supply voltages do tend to push ADCs ever closer to transducers, and most common transducers produce only millivolt signal swings. The sections which follow survey the evolution of VLSI data converter architecture over the last 10 years and offer some predictions for the next ten years. It's reasonable to speculate that data converter dynamic range improvement may slow down as we approach, say, the noise of a 50Ω resistor in a bandwidth of half the sampling frequency, but such quasifundamental limits lie beyond the next decade. View full abstract»

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  • Microsystems: A Challenge for IC Designers

    Page(s): 30 - 33
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    Micromachined mechanics, magnetics and optics allow in conjunction with microelectronics the development of various microsystems. Scaling, co-integration and introduction of arrays of sensors and actuators render the task of the designer difficult. Innovations are required at the building block and system level. View full abstract»

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  • On-Line and Off-Line Testing: From Digital to Analog, from Circuits to Boards

    Page(s): 34 - 37
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    The goal of this paper is to review the design of circuits and systems featuring testing capabilities. Those capabilities include self-checking properties necessary for on-line testing as well as BIST. The design of fail-safe reliable ASICs and boards is broadly addressed. The basic milestones over the last 25 years are reviewed and longterm perspectives are discussed. View full abstract»

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  • A -100 dB THD, 120 dB SNR programmable gain amplifier in a 3.3 V, 0.5 μm CMOS process

    Page(s): 38 - 41
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    A fully differential amplifier that operates from a 3.3V±Â±10% power-supply and featuring a -100dB THD at 2Vpp output voltage was realized. Equivalent input noise in the 100Hz - 10kHz audio-band is IμVrms, leading to a 120dB SNR. This amplifier is used as the core of a programmable gain cell in the front-end part of a ΣΔ A/D converter. The good linearity performances are achieved thanks to a novel low impedance output stage which uses a simple but efficient schematic allowing rail to rail operation on a resistive and capacitive load. Such low distortion performances actually surpasses most available test equipment and the last section explains how to deal with that fact. The technological process is 0.5μm double poly CMOS from the << centre commun >> CNET-SGS-THOMSON at Crolles, France. View full abstract»

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  • 150 MHz Preamplifier for Magneto-Resistive Heads

    Page(s): 42 - 45
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (998 KB)  

    This paper presents the read section of a 10-channel preamplifier for hard-disk-drive applications that use magneto-resistive-read/inductive-write heads. Ten dedicated low-noise amplifier stages use a current-bias current-sense architecture with grounded magneto-resistive (MR) heads. The amplifier also contains gain stages common to all heads, a high-frequency gain-boost, an MR bias current-DAC and a serial interface to program the IC. The preamplifier is designed in a 2.5 ¿m BiCMOS technology. Measurements using a single supply voltage of 3.8-5.5V show a ¿3 dB bandwidth of 120 MHz (without gain-boost) up to 180 MHz (with some gain-boost) and an input referred noise of 0.9 nV/¿Hz. View full abstract»

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  • CMOS Low-Distortion High-Frequency Variable-Gain Amplifier

    Page(s): 46 - 49
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    This paper describes the principle and design of a CMOS variable-gain amplifier for high-frequency applications. The operation of the differential circuit is based on a linear voltage-to-current conversion by means of a digitally controlled conversion impedance. Experimental results of the circuit show total harmonic distortion figures better than ¿60 dB and a gain accuracy of 0.05 dB over the ¿2 to + 12 dB gain range. View full abstract»

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  • An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops

    Page(s): 50 - 53
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    This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process. The proposed timing generator has been mapped into a 1.0 ¿m CMOS process and a RMS error of the time taps of 48 ps has been measured with a bin size of 150 ps. Used as a TDC device a RMS error of 76 ps has been obtained. View full abstract»

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  • A 10 ps Resolution 1.6 ns Tuning Range CMOS Delay Line for Clock Deskewing in Data Recovery Systems

    Page(s): 54 - 57
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    This paper describes the realization of a high resolution CMOS delay line topology. Using on-chip microstrip lines, it is possible to realize a resolution of 10 ps. Cascading 3 different delay lines gives a tuning range of more than 1.6 ns. The delay elements are digital code controlled which makes integration with the DSP in a CMOS process possible. The realized IC is designed for use in the deskewing management for a 622 Mb/s communication protocol (B-ISDN). View full abstract»

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  • A MOS Switched Capacitor Ladder Filter in SIMOX Technology for High Temperature Applications up to 300°C

    Page(s): 58 - 61
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    This paper describes techniques and methods used to realize a seventh order switched capacitor low pass filter in SIMOX technology. The filter has bessel characteristic and a 3dB-bandwidth of 20Hz at a clock frequency of 100kHz. Special design of transistors and transmission gates results in drastically reduced leakage currents. The power supply voltage is 10V. The temperature range is extended up to 300°C. Experimental results of this filter are presented. View full abstract»

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  • A 622-Mbps CMOS Bit/Frame Synchronizer for High-Speed Backplane Data Communication

    Page(s): 62 - 65
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (607 KB)  

    A new bit/frame synchronizer with optimum clock extractor and elastic serial-to-parallel (S/P) converter is presented. The circuit selects the suitable clock from equally phased multiple clocks generated by a PLL. The elastic S/P converter not only expands the bits but also recovers the frame synchronization. By our compact circuit implementation, the total hardware amount is greatly reduced. The circuit is designed for 32-input system and can handle 622Mbps with 15mW at 3.3V power supply in a 0.5-¿m CMOS process technology. View full abstract»

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