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Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European

Date 21-23 Sept. 1992

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Displaying Results 1 - 25 of 88
  • Covers

    Publication Year: 1992 , Page(s): 1
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  • Eighteenth European Solid State Circuits Conference

    Publication Year: 1992 , Page(s): I
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  • Copyright page

    Publication Year: 1992 , Page(s): II
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  • Organizing Committee

    Publication Year: 1992 , Page(s): III
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  • Programme Committee

    Publication Year: 1992 , Page(s): III
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  • Acknowledgements

    Publication Year: 1992 , Page(s): IV
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  • Foreword

    Publication Year: 1992 , Page(s): V
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  • Proceedings Table of Contents

    Publication Year: 1992 , Page(s): VI - XIV
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  • R&D in Analog Circuits: Possibilities and Needed Support

    Publication Year: 1992 , Page(s): 1 - 15
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    It is argued that the importance of analog and mixed-analog digital integrated circuits has increased in terms of volume and in terms of the number of applications, as analog circuits accompany the computer wherever the latter must interface with the real world. A number of important applications are identified, and several examples of open R&D topics are given. The context and nature of analog circuit R&D are discussed, and several factors that hinder such R&D are examined. These include some factors which are non-technical in nature but are of no lesser importance than the technical ones. View full abstract»

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  • Challenges in Testing of Mixed Mode Analog/Digital ICs

    Publication Year: 1992 , Page(s): 16 - 26
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    Testing of digital and analog ICs has became an extremely complex and often expensive activity. Testing of mixed digital/analog ICs is even more complex because of an interaction between two different environments - digital and analog - generating new failure modes. This paper examines - from a testing standpoint - basic characteristics of mixed digital/analog ICs. Out of the presented examination a possible new testing scenario, suitable for mixed ICs, is derived. It is argued that new mixed IC testing strategies must be build based on DFT techniques and that concepts successful in the digital domain must be expanded to cover entire mixed digital/analog testing arena. View full abstract»

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  • Applications of Mixed Analog/Digital Design

    Publication Year: 1992 , Page(s): 27 - 34
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    Design of a large mixed analog/digital high-performance system on a silicon chip is a challenge for any IC designer, but it can become easily a nightmare. It is, therefore, very important to know precisely what analog/digital combination means for the circuit design and performance. In this contribution, we will review fundamentals of mixed design and discuss its merits and pitfalls. View full abstract»

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  • Mixed Signal Circuits : Overview of a Flexible Design Methodology using BICMOS Processes

    Publication Year: 1992 , Page(s): 35 - 44
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    This paper describes a new design methodology for mixed signal circuits using BICMOS processes. An overview of BICMOS process requirements for mixed applications is presented as well as a new 0.7 urn CMOS and 13 Ghz/NPN process. Some innovative library concepts, which offer a lot of flexibility, are shown in the third chapter. A mixture of classical library concepts and CAD tools are extensively used. Then, an overview of a front-end arid a back-end design tool offering most of the functionality needed to develop mixed signal circuits is presented. Finally, some considerations on mixed signal circuit testing are discussed, and new tools introduced. View full abstract»

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  • Future of Battery Operated Systems

    Publication Year: 1992 , Page(s): 45
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    Summary form only given. The presentation will cover the following areas: definition of portable device; development of technology (line widths, new materials such as Si-Ge, SiC, quantum/molecular technologies); new potential device technologies (HACT, mesoscopic structures); role of new circuit technologies; technology vs. circuit design as spearhead; and examples from mobile communication. View full abstract»

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  • Industrial Application of High Level Design Tools in Large Computer System Development

    Publication Year: 1992 , Page(s): 46 - 56
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    This paper describes th current design methodologies in use at BULL SA. for the development of high range, general-purpose computers. These systems are characterized by a very complex architecture, implemented in VLSI circuits using up-to-date CMOS technologies. To meet the time to market constraints, wet defined methodologies have to be applied, guarantying a one pass zero defect design at both the functional and performance levels. Since more than 10 years, advanced design tools have been developed in the Company, to deal with the underlying design challenges. More precisely this paper presents the most innovative parts of the current methodologies, as they have been or are used by the designers. A specific emphasis is put on high level description and verification methods and tools, usable for system complexities of several millions of gates. Finally the paper contains also some prospective views on the future of high-level design tools, as they can be viewed from a mainframe manufacturer point of view. View full abstract»

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  • Analog Electronic Neural Networks

    Publication Year: 1992 , Page(s): 57 - 60
    Cited by:  Papers (3)
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    The interest in analog circuit techniques for implementing neural nets is undiminished, as is indicated by a large number of recent designs, coming from universities as well as from industry. One group of circuits are networks containing the "multiply-accumulate" neurons with a large interconnectivity. The main motivation for using analog circuit techniques is the fact that the multiply-accumulate operation can be implemented compactly, if only a moderate precision of the computation is required. Other types of networks are more algorithm-specific, hard-wired for one function, for example Kohonen networks, or neuromorphic designs implementing functions found in the visual or the auditory system. Most neural nets are built with standard CMOS technology, except for a few designs in CCD technology. A few analog neural net chips are now commercially available, and more and more reports of applications are appearing. This is a significant step in the development of analog neural nets, as now their usefulness is being put to the test in "real-world" applications. View full abstract»

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  • High-Level Design Strategies for Architectural Synthesis

    Publication Year: 1992 , Page(s): 61 - 70
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    In this paper we give an overview of state-of-the-art high-level design strategies. We introduce formal definitions of the terms high-level synthesis, behavioral synthesis, architectural synthesis, and register-transfer level synthesis. These definitions allow us to classify specification languages and synthesis systems. Furthermore, we discuss essential issues such as the impact of high-level synthesis on industrial design practice, modeling of the design space, the role of VHDL, and the hardware specification problem. To demonstrate different synthesis philosophies, we present the three synthesis systems CATHEDRAL, HIS, and CALLAS as typical examples. Each of these systems is intended for a different application domain, namely CATHEDRAL for digital signal processing algorithms, HIS for processor structures, and CALLAS for control-dominated designs. View full abstract»

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  • A Low-Power Low-Voltage Second-Order High-Pass Butterworth Leapfrog Filter

    Publication Year: 1992 , Page(s): 71 - 74
    Cited by:  Papers (1)
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    A low-power bipolar continuous-time low-frequency high-pass second-order Butterworth filter that works in the current domain and operates from a single 1.3-V battery is presented. The filter contains two adjustable integrators. These integrators are realized by means of a capacitance and an adjustable transconductance amplifier with an indirect output. The complete filter, including all capacitances needed, can be integrated in a standard full-custom IC process. A semi-custom realization is shown. The filter demonstrates operation with battery voltages down to IV with less than 16 μW power consumption and a dynamic range of 50 dB. Its cutoff frequency can be varied exponentially with a control current from 100 Hz - 1 kHz. View full abstract»

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  • Integrated Continuous-Time Balanced Filters for 16-Bit DSP Interfaces

    Publication Year: 1992 , Page(s): 75 - 78
    Cited by:  Papers (3)
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    A fully-balanced integrated continuous-time leapfrog filter, with signal linearity and dynamic range compatible with 16-bit digital audio processing, is presented. The filter employs high performance balanced op-amps and linear resistors; switchable arrays of linear capacitors controlled by a digital code perform the response tuning function. A new area efficient automatic on-chip calibrator capable of programming the response of the leapfrog filter is described. All circuitry was fabricated in a standard CMOS process. -94dB THD and dynamic range of 95dB are achieved with a 5V supply. View full abstract»

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  • A Novel SFG Structure for C-T Highpass Filters

    Publication Year: 1992 , Page(s): 79 - 82
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    This paper presents the design of a sixth order elliptic highpass filter having a passband frequency of 3.0KHz, a passband ripple of 1.0dB and a stopband attenuation of 50dB. The filter is based on a novel integrator based SFG describing a passive prototype filter; this SFG is simulated using MOSFET-C building blocks. The noise performance is considerably enhanced when compared to other highpass filter structures. Well within the stopband the output noise is dominated by amplifier noise, but only one amplifier contributes and its equivalent input noise is simply copied to the output (not amplified). Around the passband frequency MOSFET-resistor noise is the dominant noise source, but the number of MOSFET-resistors is kept at a minimum, thus reducing this noise source. The above mentioned noise properties are directly related to the new filter structure, which in addition to this has the advantage of being quite simple when compared to other integrator based highpass filter structures. View full abstract»

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  • A 2μm CMOS 5th Order Low-pass Continuous-Time Filter for Video-Frequency Applications

    Publication Year: 1992 , Page(s): 83 - 86
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    A 5th order elliptic low-pass continuous-time filter based on triode transconductors for applications in the video frequency range is presented. Fabricated in a standard 2μm CMOS technology, the filter achieves a 7 MHz cut-off frequency using a simple parasitic pole compensation scheme. A new transconductor biasing strategy is also presented, which allows the tuning of the transconductance over a decade. View full abstract»

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  • Current controlled multi-step CMOS video data converters

    Publication Year: 1992 , Page(s): 87 - 90
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    A method of connecting K identical parallel M bit converters to form a K·M bit converter is presented. By controlling the voltage drop over the resistor string with a current the linearity is made independent of offset voltage between the steps and high ONresistance in the switches. This connection gives DACs with linearity determined by the resistors and with a speed/power ratio of 15MHz/mW. An ADC based on the same idea has been developed for a PAL video application. This ADC uses two identical flash ADC blocks in the two-steps, making the principle suitable for monolithic integrated, hybrid and PCB solutions. View full abstract»

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  • A Low-Power 8 Bit 13.5 MHz Video CMOS ADC for Visiophony ISDN Applications

    Publication Year: 1992 , Page(s): 91 - 94
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    This paper describes a half-flash subranging video 13.5 MHz ADC using a new architecture which allows a flash conversion rate without any extra multiplexing comparators. View full abstract»

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  • A Stable 4th-Order Delta-Sigma Modulator with an FIR predictor

    Publication Year: 1992 , Page(s): 95 - 98
    Cited by:  Papers (1)
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    A novel approach for a stable high-order delta-sigma modulator is presented. The modulator provides 16 bit resolution at 20kHz bandwidth using 4th-order noise shaping structure at an oversampling ratio of 64. The modulation loop is completely stabilized by an FIR prediction technique. The architecture inherently has less sensitivity to component mismatch. The total hardware is much the same as the noise shaping integrators. View full abstract»

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  • A Versatile Low Power Oversampled A/D Converter

    Publication Year: 1992 , Page(s): 99 - 102
    Cited by:  Papers (5)
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    This paper presents a versatile low power oversampled A/D converter that can be either configured as a sigma delta converter or an incremental converter. The latter refers to oversampled instrumentation converters that cancel offset and 1/f noise. Versatility is achieved by keeping the design completely modular and programmable. Indeed, the implemented converter has been built with a number of identical slices, each consisting of an analog modulator and a companion digital accumulator. Programmable options are : sigma delta or incremental mode, selection of modulator order between 1 and 4, choice of oversampling factor between 2**3 and 2**18, and a comb filter order setting between 1 and 5. The proposed architecture not only leads to simpler structures. It also permits a rapid tailoring of area-optimized A/D converters to given ASIC specifications. In incremental mode, a 16 bits resolution is achieved for DC input values with an integral non-linearity error of ±20 μV. Offset and even order harmonics are cancelled to non-observable levels. The power consumption is, in this mode, 20 μA on a supply of ±2 V. View full abstract»

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  • Design of a Second Order CMOS Sigma-Delta A/D Converter with a 150 MHz Clock Rate

    Publication Year: 1992 , Page(s): 103 - 106
    Cited by:  Papers (2)
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    A continuous time filter current switching sigma delta converter operating at a frequency of 150 MHz has been developed in 2 μm CMOS technology. The design of the main components of the converter is described including a very high speed comparator, an integrator and a one bit D/A converter. Measurements show a 10 bit dynamic range with 9 bit resolution at an oversampling rate of 128. View full abstract»

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