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Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European

Date 16-18 Sept. 1985

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Displaying Results 1 - 25 of 88
  • [Cover]

    Publication Year: 1985, Page(s): 1
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  • 11th European Solid State Circuits Conference

    Publication Year: 1985, Page(s): 1
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  • Co-Sponsors

    Publication Year: 1985, Page(s): 1
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  • Steering Committee

    Publication Year: 1985, Page(s): 1
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  • Program Committee

    Publication Year: 1985, Page(s): 1
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  • Organizing Committee

    Publication Year: 1985, Page(s): 1
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  • Supporting Organizations

    Publication Year: 1985, Page(s): 1
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  • Agenda

    Publication Year: 1985, Page(s):1 - 7
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  • Table of contents

    Publication Year: 1985, Page(s): 1
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  • Limitations of Computing Devices

    Publication Year: 1985, Page(s):2 - 2c
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB)

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  • Design of a Standard Floating Point Chip

    Publication Year: 1985, Page(s):3 - 8
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  • A Pipelined 330 MHz Multiplier

    Publication Year: 1985, Page(s):9 - 12
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (955 KB)

    An 8 × 8 bit NMOS multiplier test chip for image processing systems has been realized on the basis of a newly designed carry save adder cell, a multiplication rate of 3.3 108 1/sec (fc = 330 MHz) being achieved. View full abstract»

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  • A Self Testing 2 Micron CMOS Chip Set for FFT Applications

    Publication Year: 1985, Page(s):13 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2924 KB)

    A chip set for high speed radix-2 FFT applications up to 512 points is described. The chip set comprises a (16+16)*(12+12) bit complex multiplier; and a 16 bit butterfly chip for data re-ordering, twiddle factor generation and butterfly arithmetic. The chips have been implemented using the Megacell design methodology on a 2 micron bulk CMOS process. Three chips implement a complex FFT butterfly wi... View full abstract»

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  • A Flexible High Perfomance Serial Radix-2 FFT Butterfly Arithmetic Unit

    Publication Year: 1985, Page(s):25 - 28
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    This paper describes the architecture and the design of a high performance single chip Radix-2 FFT Butterfly. The architecture is optimized to a very efficient bit-serial data processing and to a pipeline-parallel hardware structures. The design is based on a standard cell approach including LSSD test capabilities. The circuit has been fabricated at CNET (centre of Meylan Grenoble France) as part ... View full abstract»

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  • A New Family of Modular Micro-Controllers with Peripherals on Board

    Publication Year: 1985, Page(s):29 - 35
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    This paper describes a new family of modular 4-bit microcontrollers that integrate on-chip peripherals. Processed with 3 micron NMOS technology they offer very good trade-offs between speed and power consumption on one hand, cost and performance on the other hand. View full abstract»

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  • A Monolithic Dual 16 Bit D/A Converter

    Publication Year: 1985, Page(s):36 - 39
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    A monolithic dual high-speed 16 bit D/A converter is described. Each converter can be used without extra sample-and-hold or deglitcher circuitry at sampling speeds up to 200 kHz. The converter has a differential linearity of typically 0.5 LSB over a temperature range of -20 to +70°C. View full abstract»

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  • New Methods Improving Static and Dynamic Performance of an 8-Bit/120-MHz A/D Converter

    Publication Year: 1985, Page(s):40 - 44
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1179 KB)

    The step to full Nyquist operation of an 8-bit flash ADC with a sampling rate of up to 120 MHz, as reported in this paper, was achieved using new solutions for the improvement of linearity and for the compensation of signal delays. Together with a proper comparator circuit and a speed power optimized encoding structure, this led to excellent dynamic performance up to 60 MHz full scale analog signa... View full abstract»

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  • Offset and Charge Injection Compensation in an Incremental Analog to Digital Converter

    Publication Year: 1985, Page(s):45 - 48
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (887 KB)

    This paper describes a high-resolution incremental A/D converter integrated in a CMOS technology. The accuracy of the converter is independent of the precision of capacitance ratios or comparator. An autozero system cancels error sources such as the operational amplifier offset voltage and the charge injection due to the MOS transistor switches. Unlike for other MOS A/D converters, bipolar operati... View full abstract»

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  • High Speed 8-bit A/D Converter for Video Signal Processing

    Publication Year: 1985, Page(s):49 - 52
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    An 8-bit fully parallel-type A/D converter for video use has been developed. For the consumer video signal processing use, both low cost and high reliability are required. To achieve these requirements, small chip size and plastic packaging must be realized. This IC realized the smallest chip size as a bipolar A/D converter of fully parallel conversion scheme by simplifying the logic circuit and u... View full abstract»

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  • 1 GHz, 16 mW, 2 Bit Analogue to Digital GaAs Converter

    Publication Year: 1985, Page(s):53 - 56
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    There will be in the near future, a strong demand for ultra high speed, medium resolution analogue to digital (A/D) converters to be used in various field of applications such as oscilloscopy, telecommunication systems and especially radar signal processing. 8 bit, 100 MHz converters are already available in silicon technology; but the need is rather in the gigabit range which seems, at least toda... View full abstract»

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  • Table of contents

    Publication Year: 1985, Page(s): 57
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  • Integrated Cellular Array Performing Neighborhood Combinatorial Logic on Binary Pictures

    Publication Year: 1985, Page(s):58 - 63
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    We describe the design and integration of a monolithic parallel array, which performs any iteration of neighborhood combinatorial processings on binary pictures. Its main features are the small size of elementary processors (about 20 transistors only), and the combination of opto-electronic sensors and processors, which result in a compact and versatile cellular array at the picture acquisition le... View full abstract»

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  • A 2 Micron CMOS Two Dimensional Edge Detector for Real Time Image Processing

    Publication Year: 1985, Page(s):64 - 74
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (575 KB)

    A CMOS single chip edge detector capable of processing two dimensional blocks of 3 × 3 points of data to rates of 15MHz is presented. The chip has been implemented on a 2 micron bulk CMOS process, using the Megacell design methodology, the layout completed using an interactive editor with on-line design and electrical rule checking. View full abstract»

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  • High Perfomance Multitask Processor For Real Time Applications

    Publication Year: 1985, Page(s):75 - 78
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    A new high performance 16 bit NMOS microprocessor is presented which is dedicated to time critical multitask applications. A hardware implemented task scheduler allows the handling of up to 8 concurrent tasks with a medium restart latency time of 5.25 ¿s. The memory address space is 1 Moyte and the I/O space 128 bytes. High regularity in chip layout is achieved using bitslice technique in the dat... View full abstract»

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  • A Versatile High Speed Digital Signal Mixer

    Publication Year: 1985, Page(s):79 - 83
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    A circuit which performs the arithmetic function Z= K*A+(1-K)*B has been designed in a 2.5 micron CMOS process. It operates at frequencies of up to 50 MHz, allowing for example high speed digital video signal processing. The design is completely static and contains 15 pipeline levels. View full abstract»

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