Scheduled System Maintenance:
On May 6th, single article purchases and IEEE account management will be unavailable from 8:00 AM - 5:00 PM ET (12:00 - 21:00 UTC). We apologize for the inconvenience.
By Topic

Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European

Date 0-0 Sept. 1984

Filter Results

Displaying Results 1 - 25 of 73
  • [Cover]

    Publication Year: 1984 , Page(s): 1
    Save to Project icon | PDF file iconPDF (738 KB)  
    Freely Available from IEEE
  • Tenth European Solid-State Circuits Conference

    Publication Year: 1984 , Page(s): i
    Save to Project icon | PDF file iconPDF (37 KB)  
    Freely Available from IEEE
  • Foreword

    Publication Year: 1984 , Page(s): iii
    Save to Project icon | Request Permissions | PDF file iconPDF (676 KB)  
    Freely Available from IEEE
  • Organising Committee

    Publication Year: 1984 , Page(s): iv
    Save to Project icon | PDF file iconPDF (77 KB)  
    Freely Available from IEEE
  • Technical Programme Committee

    Publication Year: 1984 , Page(s): iv
    Save to Project icon | PDF file iconPDF (77 KB)  
    Freely Available from IEEE
  • Acknowledgement

    Publication Year: 1984 , Page(s): iv
    Save to Project icon | PDF file iconPDF (77 KB)  
    Freely Available from IEEE
  • Copyright page

    Publication Year: 1984 , Page(s): iv
    Save to Project icon | PDF file iconPDF (77 KB)  
    Freely Available from IEEE
  • Contents

    Publication Year: 1984 , Page(s): v - viii
    Save to Project icon | PDF file iconPDF (285 KB)  
    Freely Available from IEEE
  • Authors

    Publication Year: 1984 , Page(s): ix - x
    Save to Project icon | PDF file iconPDF (124 KB)  
    Freely Available from IEEE
  • The Impact of VLSI on Image Analysis

    Publication Year: 1984 , Page(s): 1 - 7
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2711 KB)  

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 2 μm CMOS, 10 MHz Microprogrammable Signal Processor Core with On-Chip Multiport Memory Bank

    Publication Year: 1984 , Page(s): 8 - 11
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (887 KB)  

    In this paper a 2 micron CMOS, MICROPROGRAMMABLE SIGNAL PROCESSOR CORE (SPC) is described, intended as the number crunching unit in Harvard-type digital signal processors. It contains a 16×16 bit Booth multiplier, a 40-bit accumulator, a 32 bit extractor, a format-adjuster, and a 3-port registerfile. Its projected 100 ns. throughput rate makes it highly suitable for applications like HiFi Audio, Telecom and Speech. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cornell University Signal Processor (CUSP): A VLSI High-Speed DSP CMOS Chip Exceeding VHSIC Phase I Performance

    Publication Year: 1984 , Page(s): 12 - 17
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1902 KB)  

    This paper presents the design and fabrication of the Cornell University Signal Processor (CUSP), which is a VLSI high-speed Digital Signal Processing (DSP) chip with performance exceeding the current Very High Speed Integrated Circuits (VHSIC) Phase I requirements. The current version of the CUSP to be described in this paper is a high-performance bulk CMOS processor which has been custom designed to efficiently compute a number of digital signal processing algorithms based on the Fast Fourier Transform (FFT). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Recent Developments in Integrated Sensors

    Publication Year: 1984 , Page(s): 18 - 26
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (979 KB)  

    The application of micro-electronics to non-electronic products is noticeably impeded by the lack of sensors which have a performance/price ratio comparable to that of integrated circuits. The great improvement of integrated circuits was made possible by the new processing techniques. In the first part of this paper the suitability of silicon for also making sensors will be discussed. In the second part some novel concepts, which become feasible when silicon is employed, will be described. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design Techniques for Low Noise CMOS Operational Amplifiers

    Publication Year: 1984 , Page(s): 27 - 30
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (419 KB)  

    A comparison of three different approaches on the reduction of low frequency noise in single ended CMOS operational amplifiers is made. The particular concepts are the increase of the gare areas, the chopper technique, and the Auto-Zero technique, respectively. Measured data from realized circuits as well as predicted data derived from equations are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Micropower CMOS-Instrumentation Amplifier

    Publication Year: 1984 , Page(s): 31 - 34
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (765 KB)  

    A CMOS switched capacitor instrumentation amplifier is presented. Offset is reduced by an auto-correlation technique and effects due to charge injection are attenuated by a special amplifier configuration. The circuit which is realized in a 4 ¿m double poly process has a typical offset (¿) of 370 ¿V, an RMS input referred integrated noise (0-fc/2) of 79 ¿V and consumes only 21 ¿W (fc = 8 kHz, VDD = 3 V). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full Custom LSI IC for Document Analysis Systems

    Publication Year: 1984 , Page(s): 35 - 38
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (924 KB)  

    This paper presents the architecture of a new custom IC for automatic document analysis. The circuit is to be used in the next generation of page readers which will include such items as optical character recognition (OCR) and different codings for graphics and images. The methodology used to design the circuit is also described. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Systolic Processor for a Digital Video Matrix Operator

    Publication Year: 1984 , Page(s): 39 - 42
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (972 KB)  

    The proposed VLSI circuit performs the reverse matrix transformation of the luminance and color difference eight bit coded video signals into RGB signals. The chip is composed of 3 processors each one performing the linear function XA+YB+ZC. Each processor is a systolic array based on the Baugh-Wooley two's complement parallel multiplication algorithm. The chip has been design in order to support a 18 MHz maximum clock frequency in a 3.15 micron NMOS technology, it achieves a performance figure of merit of 9.5 10 T.Hz.mm-2. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CMOS Digital Signal-Processing Codec Filter with High Performance and Flexibility

    Publication Year: 1984 , Page(s): 43 - 46
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (959 KB)  

    A novel approach for a monolithic Codec Filter is presented, which provides results for the dynamic range and the signal-to-noise ratio which exceed the CCITT requirements considerably and in addition offers very comfortable programming possibilities. Progress in circuit design simulation techniques and advanced CMOS technology made it possible to integrate the analog part and the fully digital, programmable signal processor on a single chip in an economic way. Compared to conventional Codec Filter circuits, the presented solution may further profit from the continuing reduction in feature size of VLSI technology in terms of power consumption and chip area. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Pipelined Digital Filter Chip with a Throughput Rate of 100 Mbit/s

    Publication Year: 1984 , Page(s): 47 - 50
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (861 KB)  

    A digital lowpass filter for an image coding and processing system is described. To achieve the high throughput rate (up to 100 Mbit/s) a pipeline-organization had to be used. The mapping of the filter function to a regular pipeline configuration in bit-slice technique is explained. The circuit was implemented in a standard 2 ¿m NMOS-technique. The 3.2×1.7 mm2 chip needs 3500 transistors and consumes 250 mW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Design of High Performance Analogue/Digital CMOS LSI

    Publication Year: 1984 , Page(s): 51 - 58
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    Devices available in digital oriented CMOS processes will be reviewed, with emphasis on the various possibilities of operation offered by a standard transistor, and on additional specifications required to apply devices in analogue circuits. Basic analogue circuit techniques and their related tradeoffs will then be presented with some examples, followed by a short discussion on the noisy environment due to cohabitation on chip with large digital circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Universal Adaptive Biasing Principle for Micropower Amplifiers

    Publication Year: 1984 , Page(s): 59 - 62
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (780 KB)  

    An adaptive biasing principle for differential stages is described according to which the tail current is made input-signal dependent through negative-feedback control. The control is based on a criterion which results in an optimal combination of low power consumption and high slewrate capability. Distortion properties are not degraded. The required circuitry is simple. The technique is universal in the sense that it can be applied both to bipolar and CMOS circuits; in weak as well as in strong inversion. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Monolithic Impedance Buffer, with a Compatible JFET-CMOS Technology

    Publication Year: 1984 , Page(s): 63 - 66
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (807 KB)  

    An integrated impedance buffer for microelectrodes has been designed. The circuit exhibits a low input capacitance (0.2 pF), a high driving capability and a low power consumption (750 ¿W). The circuit has been implemented in a 5 ¿m p-well CMOS technology with double implanted p-JFET-transistors for low noise performance (90 nV/VHz at 10 Hz). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Single Chip Pocket Television

    Publication Year: 1984 , Page(s): 67 - 70
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (938 KB)  

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Linear Photodiode Array with Serial and Addressable Real-Time Output Capability

    Publication Year: 1984 , Page(s): 71 - 74
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1173 KB)  

    This paper describes the design and operation of a linear photodiode array which combines a conventional serially scanned output with a parallel output capability in which any photodiode may be addressed for realtime observation. Three such arrays of 128 photodiodes each were designed in order to evaluate different novel circuit techniques. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Hard Disk Channel Processor

    Publication Year: 1984 , Page(s): 75 - 78
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (981 KB)  

    A new hard disk controller has been successfully fabricated. The operation is based on a Channel Control Word (CCW) scheme. Over 14 Mbit/s disk transfer speed was obtained. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.