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2010 IEEE Workshop on Microelectronics and Electron Devices

Date 16-16 April 2010

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Displaying Results 1 - 25 of 27
  • [Title page]

    Publication Year: 2010, Page(s): i
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  • [Copyright notice]

    Publication Year: 2010, Page(s): ii
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  • Table of contents

    Publication Year: 2010, Page(s):iii - iv
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  • Chair's message

    Publication Year: 2010, Page(s): v
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  • committee

    Publication Year: 2010, Page(s): v
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  • Technical program

    Publication Year: 2010, Page(s): vi
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  • Contributed talks

    Publication Year: 2010, Page(s):vii - viii
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  • Invited talks

    Publication Year: 2010, Page(s): viii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB) | HTML iconHTML

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Invited talks

    Publication Year: 2010, Page(s): ix
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (171 KB) | HTML iconHTML

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Invited talks

    Publication Year: 2010, Page(s): x
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (187 KB) | HTML iconHTML

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Invited talks

    Publication Year: 2010, Page(s): xi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB) | HTML iconHTML

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Invited talks

    Publication Year: 2010, Page(s): xii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (215 KB) | HTML iconHTML

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Invited talks

    Publication Year: 2010, Page(s): xiii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (199 KB) | HTML iconHTML

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Call for papers

    Publication Year: 2010, Page(s): xiv
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  • Poster presentation abstracts

    Publication Year: 2010, Page(s): xv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    Presents abstracts for the six poster presentations of this conference. View full abstract»

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  • Modified Floating Gate and IPD Profile for Better Cell Performance of Sub-50 nm NAND Flash Memory

    Publication Year: 2010, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (474 KB) | HTML iconHTML

    We report a new approach to utilize oxygen implantation on the top of the floating gate (FG) to improve the cell performance of a sub-50 nm NAND flash memory cell. This method was used to form a thin oxide layer only on the top of the FG but not on the sidewalls. It also rounded the corners of the FG. As a result, the leakage current between FG and control gate (CG) was reduced without sacrificing... View full abstract»

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  • Study of Carrier Mobility of Low-Energy, High-Dose Ion Implantations Using Continuous Anodic Oxidation Technique/Differential Hall Effect (CAOT/DHE) Measurements

    Publication Year: 2010, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB) | HTML iconHTML

    New carrier mobility (¿) data for boron-, phosphorus-, and arsenic-doped Si in a low-energy, high-dose implant regime are measured and studied using continuous anodic oxidation technique/differential Hall effect (CAOT/DHE) technique. The data show that when the doping concentration is > 1020/cm3, both hole and electron mobility values are lower than the conventional model... View full abstract»

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  • Discrete Test Structure Device Degradation Analysis and Correlation to NAND Flash Circuit Operation

    Publication Year: 2010, Page(s):1 - 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (259 KB) | HTML iconHTML

    A methodology is established to correlate shifts of test structure device parameters, due to device degradation or process variation, to circuit operation throughout the product lifetime. To the authors' knowledge, this work is original in that SPICE simulation is used, with degraded device models, to relate a circuit timing metric to the degradation of a discrete device used in the circuit. The c... View full abstract»

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  • A Comprehensive Study on Nanomechanical Properties of Various SiO2-Based Dielectric Films

    Publication Year: 2010, Page(s):1 - 4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (421 KB) | HTML iconHTML

    This paper studies the nanomechanical properties, including hardness and Young's modulus (both in a dry condition and in deionized water), fracture toughness, cohesive strength and scratch resistance of eight commonly used SiO2-based dielectric films, Boron Phosphosilicate Glass (BPSG), BPSG with Rapid Thermal Processing (RTP), Phosphosilicate Glass (PSG), Spin-On Dielectric (SOD), Plas... View full abstract»

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  • A Novel Depletion Mode High Voltage Isolation Device

    Publication Year: 2010, Page(s):1 - 3
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (283 KB) | HTML iconHTML

    A novel depletion mode high voltage isolation device is presented. It consists of a narrow n- resistor covered with a grounded metal field plate. This device will pass low voltages, but will block high voltages. It has potential application to isolate a NAND memory array from periphery low voltage circuitry, and has the benefit that it can be made more compact than a standard MOSFET device and can... View full abstract»

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  • Fullband Study of Ultra-Scaled Electron and Hole SiGe Nanowire FETs

    Publication Year: 2010, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1757 KB) | HTML iconHTML

    Ultra-scaled SiGe nanowire FETs (NWFETs) are an attractive candidate in achieving faster p-type devices compared to Silicon. This work investigates the performance of SiGe nanowire FETs (NWFETs) using a Virtual Crystal Approximation (VCA) method based on an atomistic Tight-Binding (TB) model. The electronic structure calculation is self- consistently coupled to a 2D Poisson solver. The spatial cha... View full abstract»

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  • Continuous-Time/Discrete-Time (CT/DT) Cascaded Sigma-Delta Modulator for High Resolution and Wideband Applications

    Publication Year: 2010, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB) | HTML iconHTML

    This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topo... View full abstract»

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  • All Digital Multiplying DLL Using Precision Digital Delay Line as DCO

    Publication Year: 2010, Page(s):1 - 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    In this paper all digital multiplying delay-locked loop (MDLL) is presented, which uses a 3rd order precision digital delay line (HDL) as DCO. Maximum locking frequency at 1.3 V was 1 GHz with multiplication factor of 50, assuming 20 MHz reference clock frequency, and peak to peak jitter was ± 61617; 20ps. DCO consumed only 2.2 mW, and the rest logic 3.5 mW. View full abstract»

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  • Main Memory with Proximity Communication: A Wide I/O DRAM Architecture

    Publication Year: 2010, Page(s):1 - 4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (355 KB) | HTML iconHTML

    The bandwidth and power consumption of dynamic random access memory (DRAM), used as the main memory of a computer system, impacts computer execution rates. DRAM manufacturers focus on density increases, due to the innate price per bit decline of main memory, while processor manufacturers continually focus on boosting performance. This leads to a performance gap between the two technologies. Proxim... View full abstract»

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  • A Low Noise Low Power DC Coupled Sensor Amplifier with Offset Cancellation

    Publication Year: 2010, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (261 KB) | HTML iconHTML

    A 16-channel sensor amplifier was designed in the Jazz 0.18 ¿m CMOS process. The sensor amplifier has programmable gain from 20 to 2000 and a DC offset cancellation of ±0.3 V using bulk voltage control. A charge pump, band gap reference and a resistor string DAC were designed for bulk voltage control. Input referred noise of 0.465 ¿V was achieved at a gain of 2000. The power required per channe... View full abstract»

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