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Quality Electronic Design (ISQED), 2010 11th International Symposium on

Date 22-24 March 2010

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Displaying Results 1 - 25 of 146
  • [Front cover]

    Page(s): c1
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  • [Spine]

    Page(s): 1
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  • [Title page]

    Page(s): i
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  • [Copyright notice]

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  • ISQED quality Award recipient (IQ-Award 2010)

    Page(s): iv
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  • ISQED 2010 best papers

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  • SQED 2010 Organizing Committee

    Page(s): vi - xi
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  • ISQED 2010 fellow Award recipient

    Page(s): xii
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  • ISQED 2010 - table of contents

    Page(s): xiii - xix
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  • Call for papers

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  • Preliminary call for papers

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  • Notes [blank page]

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  • Limits of bias based assist methods in nano-scale 6T SRAM

    Page(s): 1 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (397 KB) |  | HTML iconHTML  

    Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Large scale 6T SRAM arrays beyond 65 nm will increasingly rely on assist methods to overcome the functional limitations imposed by increased variation, reduced overdrive and the inherent read stability/write margin trade off. Factors such as reliability, leakage and data retention establish the boundary conditions for the maximum voltage bias permitted for a given circuit assist approach. These constraints set an upper limit on the potential yield improvement that can be obtained for a given assist method and limit the minimum operation voltage (Vmin). By application of this set of constraints, we show that the read assist limit contour (ALC) in the margin/delay space can provide insight into the ultimate limits for the nano-scale CMOS 6T SRAM. View full abstract»

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  • Variability resilient low-power 7T-SRAM design for nano-scaled technologies

    Page(s): 9 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (593 KB) |  | HTML iconHTML  

    High variability in nano-scaled technologies can easily disturb the stability of a carefully designed standard 6T-SRAM cell, causing access failures during a read/write operation. We propose a 7T-SRAM cell to increase the read/write stability under large variations. The proposed design uses a low overhead read/write assist circuitry to increase the noise immunity. Use of an additional transistor and a floating ground allows read disturb free operation. While the write assist circuitry provides a floating ground during a write operation that weakens cell storage by turning off the supply voltage to ground path of the cross-coupled inverter pair. This allows a high speed/low power write operation. Monte Carlo simulations indicate a 200% increase in the read stability and a boost of 124% in write stability compared to a conventional 6T-SRAM design, when subjected to random dopant fluctuations, line edge roughness, and poly-granularity variations. HSPICE simulations of a 45nm 64×32 bit SRAM array designed using standard 6T and proposed 7T SRAM cells indicate a 31% improvement in write speed/write power, read power decreases by 60%, and a 44% reduction in the total average power consumption is achieved with the proposed design. View full abstract»

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  • Robust importance sampling for efficient SRAM yield analysis

    Page(s): 15 - 21
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8684 KB) |  | HTML iconHTML  

    Monte Carlo simulations have been widely adopted for analyzing circuit properties, such as SRAM yield, under strong influence of process variations. Enormous calculation time is required in such a simulation due to the low defect probabilities. In this paper, we propose a robust shift-vector determination for mean-shift importance sampling, by which efficiency and stability of the Monte Carlo simulation is improved. In the proposed method, the hypersphere sampling is developed to autonomously find the optimal shift-vector. The sampling is also limited to the regions where meaningful contribution to the yield is recognized. Simulation examples reveal that the proposed technique stably and efficiently estimates yield of noise stabilities of an SRAM cell. At the failure probability of 10-10, the number of calculation trials has been reduced by six orders magnitude compared with a conventional Monte Carlo simulation. View full abstract»

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  • An accurate modeling method utilizing application-specific statistical information and its application to SRAM yield estimation

    Page(s): 22 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    In this paper, we propose a new model construction method utilizing application specific physical information and present its application to SRAM yield calculation. The physical information is extracted as statistical distributions from past simulation results automatically. Experimental results show our method achieves 700x speed up over non modeling method and more than 10x speed up over the conventional modeling method. It requires only 5.3 samples to model a fifth order full cross term polynomial with 21 coefficients and is free from over-fitting and singular matrix problem. This modeling method can be a general approach to create models with application specific physical information. View full abstract»

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  • Adaptive power gating for function units in a microprocessor

    Page(s): 29 - 37
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    This paper describes adaptive fine-grain control to power gate function units based on temperature dependent break-even time (BET). An analytical model to express the temperature dependent BET is introduced and the accuracy of the model was examined. Results demonstrated that the model well represents the exponential decrease in BET with the temperature. Meanwhile, it was found that the accuracy gets worse at higher temperature and the cause is energy dissipation due to transient glitch at the wakeup. We propose four power-gating policies employing time-based or history-based approaches. Effectiveness in energy savings was evaluated using real design data of four function units in a microprocessor implemented in a 65 nm technology. Results showed that introducing adaptive control to make use of temperature-dependent BET enhances energy savings by up to 21% in the time-based approach and by up to 18% in the history-based approach. The adaptive history-based policy with a limiter outperforms the adaptive time-based policy in energy savings and reduces the total energy of four function units to 11.8% at 100°C as compared to the non-power-gating case. View full abstract»

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  • A dual-level adaptive supply voltage system for variation resilience

    Page(s): 38 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB) |  | HTML iconHTML  

    VLSI circuits of 45 nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where the negative effect of variations is strong. We propose a dual-level ASV system for designs containing many timing critical paths. This system can simultaneously provide adaptive supply voltage at both coarse-grained and fine-grained level, and has limited power routing overhead. The dual-ASV system is compared with conventional ASV through SPICE simulations on benchmark circuits. The results indicate that the dual-ASV system consumes significantly less power and achieves similar performance in presence of variations. View full abstract»

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  • A low power charge-redistribution ADC with reduced capacitor array

    Page(s): 44 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (733 KB) |  | HTML iconHTML  

    This paper presents a novel design of low power charge redistribution successive approximation analog to digital converter (CR-SAR ADC). During its conversion, the voltage swing of the capacitor array is reduced to half of the voltage reference without decreasing the ADC dynamic range. The reduced voltage swing results in a significant reduction of ADC power consumption. Also, the proposed design requires only half of the total capacitance that is used in a traditional CR-SAR ADC with the same resolution. MATLAB simulations are performed to compare the power consumption due to charging the capacitor array in the proposed and previous low power CR-SAR ADC'S. The proposed circuit is implemented using a 0.13¿ CMOS technology. Post-layout simulation shows that the proposed converter consumes 63% less energy compared to a traditional CR-SAR ADC. View full abstract»

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  • Leakage current analysis for intra-chip wireless interconnects

    Page(s): 49 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6302 KB) |  | HTML iconHTML  

    A simulation-based feasibility study of an intra-chip wireless interconnect system is presented. The wireless interconnect system is modelled in a 250 nm standard complementary metal-oxide semiconductor (CMOS) technology operating at typical conditions. A finite element method (FEM) based 3-D full-wave solver is used to perform the electromagnetic field analysis. In the field analysis, the effects of the radiation of an intra-chip wireless interconnect system operating at 16 GHz on the circuit devices and local metal interconnects at arbitrary distances from the antennas are investigated. It is shown that the transmission gain between the antennas is mostly unaffected by the presence of local metal interconnects. The transmission scattering parameter (s-parameter) between the radiating antenna and the metal interconnects is below -31.66 dB. The leakage current in the sub-threshold region of the transistors, caused by the antenna radiation induced voltages, is shown to be below 2.2 fA and decreasing with distance from the radiating antenna. View full abstract»

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  • Toward effective utilization of timing exceptions in design optimization

    Page(s): 54 - 61
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9951 KB) |  | HTML iconHTML  

    Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-functional critical paths. Ideally, timing exceptions should always be helpful for quality of results (QOR) metrics such as area or number of timing violations, and for design turnaround time (TAT) metrics such as tool runtime and number of design iterations. We expect this positive impact since timing exceptions reduce the number of constraints that the design optimization must satisfy. In this work, we evaluate the impact of timing exceptions on design QOR and TAT, with respect to (1) the forms in which timing exception are declared, (2) the timing criticality of the target paths, (3) the number of applicable exceptions, and (4) the design stages at which timing exceptions are extracted and applied. From our experimental analyses, we observe that applying more exceptions in commercial tool flows does not consistently lead to better QOR, and often only increases runtime unnecessarily. We analyze potential causes of unwanted impacts of timing exceptions, and examine various methods to filter out ineffective timing exceptions. Implications of our study give preliminary guidelines for designers and EDA vendors regarding the use of timing exceptions in design optimization processes. Our work hopefully lays a foundation for novel design methodologies that can maximize the benefits of timing exceptions. View full abstract»

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  • Useful clock skew optimization under a multi-corner multi-mode design framework

    Page(s): 62 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3748 KB) |  | HTML iconHTML  

    As VLSI technology scales into sub-65 nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner multi-mode design, some more efficient methods need to be invented. In this work, we propose to address such a kind of issue by exploiting useful clock skew, which can help reduce timing violations rapidly. We also add mode/corner metric balancing measurements to make this method more flexible and applicable especially in such deep stages while the CTS is ready. The results indicate that our method can achieve an average improvements of 33.16% on the worst slack (WS) and 75.56% on the total negative slack (TNS), respectively. View full abstract»

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  • Clock buffer polarity assignment considering the effect of delay variations

    Page(s): 69 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (218 KB) |  | HTML iconHTML  

    This work addresses the problem of minimizing power/ground noise with an important design parameter, which is the delay variations on the clock tree. Without considering the effect of delay variations on the polarity assignment, the resulting statistical clock skew may lead to a high probability of skew violation, which causes a low yield of design. Given distributions on the delay of each type of buffering elements and the interconnect delay from the clock source to every flip-flop with spatial delay correlations, and the clock skew and yield constraints, we solve the problem of assigning polarity to each sink buffer (i.e., assigning a buffering type) so that the power/ground noise is minimized while satisfying the yield and clock skew constraints. Specifically, we solve the problem in two steps where in step 1, for each pair of sinks a set of feasible combination(s) of polarities to the sinks that do not violate the yield constraint as well as the clock skew constraint is extracted, and in step 2, a stepwise greedy method is applied to determine the polarities to sinks from the feasible sets obtained in step 1 to minimize the power/ground noise. Through experiments with ISCAS89 benchmark circuits, it is shown that our proposed approach is able to improve yield by 6.7% on average even with 4.3% less power and 4.4% less ground noises over the results by the conventional polarity assignment approach which does not consider the delay variations. View full abstract»

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  • Linear time calculation of state-dependent power distribution network capacitance

    Page(s): 75 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7311 KB) |  | HTML iconHTML  

    A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The proposed tool facilitates to study capacitance variation, which is necessary to build an accurate macro model of an LSI. View full abstract»

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