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Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Date 12-15 May 1991

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  • Proceedings of the IEEE 1991 Custom Integrated Circuits Conference (Cat. No.91CH2994-2)

    Publication Year: 1991
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    Freely Available from IEEE
  • Mixed mode simulation of slow transient effects in AlGaAs/GaAs HEMT inverters

    Publication Year: 1991 , Page(s): 4.6/1 - 4.6/4
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    A mixed level device and circuit analysis has been performed to study the DX-trap-induced slow transient effects on the performance degradation of AlGaAs/GaAs HEMT (high electron mobility transistor) circuits. The variation of the output pulse width and the hysteretic characteristics of the input-output voltage transfer function in DCFL (direct coupled FET logic) HEMT inverters have been simulated. It is shown that the output pulse broadening phenomena in a string of cascaded DCFL HEMT inverters are a consequence of the inverter voltage transfer function shift caused by deep traps View full abstract»

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  • Technology- and power-supply-independent cell library

    Publication Year: 1991 , Page(s): 25.5/1 - 25.5/4
    Cited by:  Papers (8)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    The authors present a novel principle for the design of digital CMOS cell libraries. All the cells are made of branches (1 to 3 MOS in series), providing the possibility of describing only a few very simple branch models that can be parameterized by the power supply and by different technologies. All the cells are exclusively made of branches that contain one or several transistors in series connected between a power line and a logical node. This concept was originally used for a gate-matrix layout system View full abstract»

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  • A 1.5 MLIPS 40-bit AI processor

    Publication Year: 1991 , Page(s): 15.3/1 - 15.3/4
    Cited by:  Papers (2)
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    A high-performance 40-bit AI (artificial intelligence) processor with a capability of 1.5 MLIPS (mega-logical-inference per second) in append has been developed. The performance of this processor is achieved by the combination of novel architectures of pipelined data typing and dereference, a 0.8-μm CMOS technology, and a clock scheme View full abstract»

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  • Optimization of field-programmable gate array logic block architecture for speed

    Publication Year: 1991 , Page(s): 6.1/1 - 6.1/6
    Cited by:  Papers (22)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    The authors explore the effect of the choice of logic block on the speed of a field-programmable gate array (FPGA). A set of logic circuits was implemented as FPGAs, each using a different logic block, and the speed of the implementation was measured. While the result depends on the delay of programmable routing, experiments indicate that wide input PLA (programmable logic array)-style AND-OR gates, four- and five-input lookup tables, and certain multiplexer configurations produce the lowest total delay over the important values of routing delay. Furthermore, significant gains in performance (from 10% to 41% reduction in total delay) can be achieved by connecting a small number of logic blocks together using hard-wired connections View full abstract»

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  • A 14 bit CMOS A/D converter based on dynamic current memories

    Publication Year: 1991 , Page(s): 24.2/1 - 24.2/4
    Cited by:  Papers (11)
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    Dynamic current memories allow the realization of accurate cyclic or pipeline A/D converters without requiring floating capacitors while being insensitive to linearity, hysteresis, and matching of components. A cyclic A/D converter based on this principle has been integrated in a 3-μm CMOS technology and exhibits a 14-bit linearity. The authors present fundamental limits in terms of speed, accuracy, and noise of cyclic (pipeline) converters based on dynamic current memories. Limiting factors for the accuracy are mainly the charge injection in the gate storage capacitance, and the output conductance of the MOS current memory. Charge injection is minimized by using carefully designed compensation switches and by controlling some gate voltages. The effect of the output conductance is reduced by using a cascode transistor whose drain voltage is controlled by a current conveyor View full abstract»

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  • Characterizing a VLSI standard cell library

    Publication Year: 1991 , Page(s): 25.7/1 - 25.7/4
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    The author describes a set of procedures for maintaining and characterizing an ASIC (application-specific integrated circuit) standard cell library. A modular set of programs that generate timing parameters and associated documentation in a well-integrated design environment has been developed. Input to the system is ideally a layout description in GDSII format; its outputs are direct interfaces to the logic simulator and a data sheet for documentation purposes which is further processed by TROFF. The advantage of the proposed approach compared to other systems is the separation of the stimuli databases from the process of parameter extraction. Another advantage is the flexibility of the approach View full abstract»

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  • The architecture of the GenTest sequential test generator

    Publication Year: 1991 , Page(s): 17.1/1 - 17.1/4
    Cited by:  Papers (16)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    GenTest is an automatic test pattern generator for sequential circuits. There are few constraints on the circuit, and scan design is not required. GenTest consists of the STG3 test generator and the DSIM differential fault simulator. The architecture of GenTest is described in detail, including the test generator, the embedded fault simulator, and the models of sequential elements used. GenTest has recently been extended to support test generation for circuits to be tested using current monitoring or IDDQ. Results of runs on the ISCAS'89 benchmarks are provided View full abstract»

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  • A high speed BiCMOS table look-up gate

    Publication Year: 1991 , Page(s): 6.3/1 - 6.3/4
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    The authors describe a BiCMOS programmable gate array (PGA) with subnanosecond logic block delay and low power consumption. Each logic block can implement any Boolean function of three inputs, a D-latch, or an SR-latch. The PGA is supported by an advanced design environment, which includes schematic capture, interactive functional simulation, logic minimization, and technology mapping View full abstract»

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  • Fully-differential CMOS current-mode circuits

    Publication Year: 1991 , Page(s): 24.1/1 - 24.1/4
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    A CMOS fully-differential current-mode analog signal processing technique has been developed. The basic building block, a 5-V fully differential current-mode operational amplifier (I-OPAMP), has been integrated using the MOSIS 2 μm n-well CMOS technology. Measured total harmonic distortion (THD) is -70 dB with a peak signal to bias current ratio of 0.5. By simply adding MOS switches, the I-OPAMP topology is easily extended to implement fully differential switched-current (SI) circuits with first-order cancellation of clock-feedthrough effects. A five-pole Chebyshev lowpass fully differential SI ladder filter has also been integrated in the 2-μm p-well CMOS technology. Measured results show that, with a sampling frequency of 128 kHz, the desired ripple bandwidth of 5 kHz is accurately realized using the fully differential SI structure. Dynamic range is greater than 80 dB with a power dissipation of 14 mW View full abstract»

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  • A CMOS biquad at VHF

    Publication Year: 1991 , Page(s): 9.1/1 - 9.1/6
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    A differential transconductance-C biquad implemented in the digital subset of a 0.9-μm CMOS process operates at frequencies up to 450 MHz and Q-factors to approximately 100 with SNR (signal-to-noise ratio) in the range of 35-45 dB. By switching in capacitors and adjusting control voltages it can be tuned to below 30 MHz, demonstrating the capability of operating over the entire VHF range. The active area is 0.029 mm2 and power consumption is 30 mW View full abstract»

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  • A CMOS 4 ch×1 k time memory LSI with 1 ns resolution

    Publication Year: 1991 , Page(s): 10.5/1 - 10.5/4
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    A four-channel 1024-b time-to-digital converter chip which records input signals to memory cells at 1-ns intervals, has been developed. The chip was fabricated using 0.8-μm CMOS technology on a 5-mm by 5.6-mm die. It dissipates only 7 mW/channel under typical operating conditions. Tests show that overall linearity and stability are very good View full abstract»

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  • An analytical-model generator for interconnect capacitances

    Publication Year: 1991 , Page(s): 8.6/1 - 8.6/4
    Cited by:  Papers (12)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    A tool for automatically generating analytical models of interconnect capacitances is presented. It uses a partial knowledge of the flux components associated with a configuration to choose a suitable form of analytical expression, and then uses curve-fitting techniques to obtain the analytical models. For each coupled configuration, the form for the coupling capacitance is chosen based on a decomposition of the mutual flux associated with the two lines. The form for the correction capacitance of each line is decided based on a decomposition of its flux intercepted by the other line. A design-parameter-based modeling is pursued, since often it is desired to perform a large number of evaluations of a capacitance in a layout, with a fixed set of process parameters, but for varying values of design parameters. The configurations which are currently considered by this model generator are a single line, crossing lines, parallel lines on the same layer, and parallel lines on different layers (both overlapping and nonoverlapping) View full abstract»

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  • A 50 MHz variable gain amplifier cell in 2 μm CMOS

    Publication Year: 1991 , Page(s): 9.4/1 - 9.4/3
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    A CMOS variable gain amplifier is described for possible use in disk drive read channels. The 0.9 mm2 cell attains a 30-dB range of variable gain with a 50-MHz bandwidth, requires a single 5-V supply, and dissipates 150 mW View full abstract»

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  • A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2-μm CMOS for 2B1Q high bit-rate digital subscriber line transceivers

    Publication Year: 1991 , Page(s): 7.2/1 - 7.2/4
    Cited by:  Papers (3)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    A 60-MHz 64-tap adaptive FIR filter chip has been fabricated in 1.2-μm CMOS which can implement either an echo canceller or decision-feedback equalizer for 2B1Q high bit-rate digital subscriber line (HDSL) transceivers. The 4.3-mm×4.3-mm, 30000-transistor chip is a complete self-contained adaptive filter which incorporates the LMS algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths which are often required in high-bit-rate transceivers. At a 60-MHz clock rate the echo canceller/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud View full abstract»

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  • 100 Mpixel/sec single-chip integrated graphics controller (IGC)

    Publication Year: 1991 , Page(s): 16.5/1 - 16.5/4
    Cited by:  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    The IGC, a single-chip 2-D raster graphics engine for 1-2-Mpixel, 8-bit pseudorealistic color desktop systems, is described. With on-chip controllers for video, RAMDAC, and interleaved VRAMs, together with dedicated hardware for scan-conversion, image and block transfers, clipping, and raster operations, the 185 K transistor, 208-pin custom IC operates at 25 MHz at full 1-Mbit VRAM bandwidth of 100 Mpixel/s. The IGC eliminates the performance bottleneck of workstations and personal computers by performing graphics functions at the maximum bandwidth of the interleaved pixmap with a minimum amount of support hardware View full abstract»

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  • A sub-micron CMOS embedded SRAM compiler

    Publication Year: 1991
    Cited by:  Papers (3)  |  Patents (1)
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    The authors describe the Memorist SRAM compiler, a highly flexible memory generation system that produces high-speed, high-density synchronous single or dual port static diffused memories embedded in a gate array environment. It provides for accurate timing characterization and is lightly integrated into an ASIC (application-specific integrated circuit) development system. Embedded memories up to 256K bits can be achieved View full abstract»

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  • A modular flash EEPROM technology for 0.8 μm high speed logic circuits

    Publication Year: 1991 , Page(s): 18.7/1 - 18.7/4
    Cited by:  Papers (3)  |  Patents (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    A flash EEPROM technology has been integrated into a 0.8 μm double-metal CMOS high-speed process for custom integrated circuit applications. The modular approach employed effectively decouples the double-poly, thick-oxide flash EEPROM process from the single-poly, thin-oxide host process. The flash EEPROM has a <100-μs byte programming time and a nominal 1-s bulk erasure time. The low threshold voltage of the erased cell permits access without wait states at 3-V supply. This technology has been successfully demonstrated on a 32-b microcontroller with a 32-kbyte flash EEPROM module View full abstract»

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  • A 0.8-μm BiCMOS sea-of-gates implementation of the tandem banyan fast packet switch

    Publication Year: 1991 , Page(s): 3.3/1 - 3.3/6
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    A simple, high-performance architecture for fast packet switching, called the tandem banyan switching fabric, has been proposed. The authors report on the implementation of the routing functionality of this architecture, augmented with self-testing and fault-recovery capabilities, using a high-performance BiCMOS sea-of-gates on a 0.8-μm technology View full abstract»

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  • 1 GHz CMOS 12:1 time division MUX/DEMUX pair

    Publication Year: 1991 , Page(s): 3.5/1 - 3.5/4
    Cited by:  Papers (6)
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    A 1-GHz 12:1 MUX/DEMUX (multiplexer/demultiplexer) pair has been designed and fabricated in 0.9-μm CMOS technology. They work with input clock amplitudes as low as 1.0 V. The skew between the clock and high-speed data to DEMUX can vary as much as 700 ps. The MUX drives up to 50 mA of current into the equivalent of a 25-Ω load with rise/fall times of ~200 ps. The pair was tested in package form, yielding a 0 bit error rate with pseudorandom data up to 900 MHz. Full custom cells were used in the high-speed section, and standard cells were used for the low-speed section View full abstract»

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  • A pipelined 9-stage video-rate analog-to-digital converter

    Publication Year: 1991 , Page(s): 26.4/1 - 26.4/4
    Cited by:  Papers (11)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    The authors describe a nine-stage, pipelined, video-rate, analog-to-digital converter (ADC) in a 0.9-μm CMOS technology. At a conversion rate of 20 Msamples/s, the converter has 10-b resolution, 56-dB signal-to-noise-and-distortion ratio (SNDR) with a 100-kHz input, and 54-dB SNDR with a 5-MHz input. It occupies 9.3 mm2 and dissipates 300 mW. The key innovation in this ADC is the improved correction algorithm, which requires one fewer comparator per stage than used in traditional architectures View full abstract»

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  • Automatic custom layout of analog ICs using constraint-based module generation

    Publication Year: 1991 , Page(s): 5.5/1 - 5.5/4
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    A systematic method for automatic custom layout of analog integrated circuits is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. Constraint-driven analog floorplanning and routing techniques are developed to generate custom layouts which incorporate the layout constraints. This method can be applied to handle a wide variety of analog circuit modules as well as analog subsystems. Experimental results on CMOS operational amplifiers and a comparator are presented View full abstract»

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  • A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

    Publication Year: 1991 , Page(s): 27.2/1 - 27.2/4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structure is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown View full abstract»

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  • 2-10 MHz programmable continuous-time 0.05° equiripple linear phase filter

    Publication Year: 1991 , Page(s): 9.5/1 - 9.5/4
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    The authors present a bipolar monolithic seventh-order 0.05° equiripple linear phase transconductance-capacitor lowpass filter with a cutoff frequency (fc) tunable between 2 and 10 MHz. Programmable equalization up to 9 dB at fc is also provided. Total harmonic distortion at 2 Vpp is less than 1%. Nominal power consumption from a single 5-V supply is 135 mW. The circuit also has a low power mode (<5 mW dissipation) View full abstract»

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  • Strategies for CMOS/BiCMOS gate usage on sea-of-gates arrays

    Publication Year: 1991 , Page(s): 14.2/1 - 14.2/4
    Cited by:  Papers (6)
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    Strategies for merging CMOS and BiCMOS gates on a sea-of-gates (SOG) array are analyzed. Starting from theoretical and experimental distributions for load capacitance and gate complexity, the average delay and area and the optimal percentage of each gate type can be calculated. From those results, the optimal bipolar-to-MOS count ratio of a BiCMOS SOG master can be derived. Advanced gate usage strategies mixing simple and buffered CMOS and BiCMOS gate configurations are shown to be significantly superior in terms of speed and density. For typical capacitance distributions, the speed advantage can be as high as 70% compared to a pure BiCMOS solution View full abstract»

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