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Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on

Date 13-15 Jan. 2010

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Displaying Results 1 - 25 of 68
  • [Front cover]

    Page(s): C1
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  • [Title page i]

    Page(s): i
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  • [Title page iii]

    Page(s): iii
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  • [Copyright notice]

    Page(s): iv
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  • Table of contents

    Page(s): v - x
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  • Message from the General Chairs

    Page(s): xi
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  • Message from the Technical Program Chairs

    Page(s): xii
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  • Organizing Committee and Reviewers

    Page(s): xiii - xvi
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  • Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs

    Page(s): 3 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB) |  | HTML iconHTML  

    Built-in self-repair (BISR) is one promising approach for improving the yield of memory cores in an system-on-chip (SOC). This paper presents a test scheduling approach for BISR memory cores under the constraint of maximum power consumption. An efficient test scheduling algorithm based on the early-abort probability is proposed. Experimental results show that the scheduled results of the proposed algorithm have lower expected test time in comparison with the previous work. For ITC'02 benchmarks, for example, about 10.7% average reduction ratio of expected test time can be achieved by the proposed algorithm. View full abstract»

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  • (Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems

    Page(s): 8 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1267 KB) |  | HTML iconHTML  

    This paper presents an overview of test techniques that offer promising features when Built-In-Self-Test (BIST) must be applied to complex integrated systems including analog, mixed-signal and RF parts. Emphasis is on techniques exhibiting a good trade-off between test requirements (basically in terms of signal accuracy and frequency) and test quality. View full abstract»

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  • Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits

    Page(s): 14 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    In this paper, a new very fast fault simulation method for extended class of faults is proposed. The method is based on a two-phase procedure. In the first phase, a novel parallel exact critical path fault tracing is used to determine all the "active" nodes with detectable stuck-at faults. In the second phase of the procedure, reasoning is carried out to determine the detectable physical defects based on the information about the "active" nodes and the current (or previous) logic state of the network. View full abstract»

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  • Enabling False Path Identification from RTL for Reducing Design and Test Futileness

    Page(s): 20 - 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB) |  | HTML iconHTML  

    Information on false paths is useful for design and test. Since identification of false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established only by some restricted logic synthesis. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis. View full abstract»

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  • Least-squares Optimal Interpolation for Fast Image Super-resolution

    Page(s): 29 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1736 KB) |  | HTML iconHTML  

    Image super-resolution is generally regarded as consisting of three steps - image registration, fusion, and deblurring. This paper presents a novel technique for resampling a non-uniformly sampled image onto a uniform grid that can be used for fusion of translated input images. The proposed method can be very fast, as it can be implemented as a finite impulse response filter of low order (10th order results in good performance). The technique is based on optimising the resampling filter coefficients using a simple image model in a least squares fashion. The method is tested experimentally on a range of images and shown to have similar results to that of a least-squares optimal filter. Further experimental comparisons are made against a number of methods commonly used in image super-resolution that show that the proposed method is superior to these. View full abstract»

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  • Design, Fabrication and Characterization of Asymmetric Fabry-Perot Modulator for Large Size Optical Shutter

    Page(s): 35 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (966 KB) |  | HTML iconHTML  

    We report the growth, fabrication and characterization of asymmetric Fabry-Perot modulators which function as optical shutter which can be used in 3-D imaging. By choosing appropriate electrode geometry, a reduction in parasitic capacitance was achieved. The results reveal that such devices are promising candidates as optical shutter for 3-D imaging applications. View full abstract»

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  • A Hybrid CMOS DPS with Conditional Data Readout Scheme

    Page(s): 44 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1077 KB) |  | HTML iconHTML  

    In this paper, a hybrid CMOS pulse width modulation (PWM) digital pixel sensor (DPS) is proposed. In order to reduce the pixel area, the proposed architecture requires only a two bit on-pixel memory while placing the remaining six bits outside the array, assuming a common resolution of eight bits. This new architecture reduces the size of the pixel significantly as the memory requirement at pixel level is divided by 4. The eight bit resolution is maintained by scanning the array of pixels periodically during the integration period. In addition, a conditional data readout scheme is proposed in order to reduce the unnecessary read operations of pixel-level memories. Therefore, switching activity of data buses and dynamic power are kept under control. In our implementation, the pixel contains only 21 transistors and occupies an area of about 9¿m × 9¿m, with a fill factor of 12% using a 0.18¿m CMOS process. Simulation results show a 50% reduction of read bit-lines switching activity at low illumination conditions, using our conditional readout scheme. View full abstract»

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  • A 75dB-gain Low-power, Low-noise Amplifier for Low-frequency Bio-signal Recording

    Page(s): 51 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (306 KB) |  | HTML iconHTML  

    This paper presents a low voltage, low noise and very low frequency amplifier suitable for bio-signal recording. The amplifier requires only ±0.6 V supply and consumes 1.24 ¿W, with a 75.5 dB gain over a bandwidth covering a range of frequencies from some hundreds of mHz to 19 kHz. A UMC 0.13 ¿m CMOS process is used in design and simulation. The new solution is suitable for a variety of biomedical applications. View full abstract»

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  • A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques

    Page(s): 54 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB) |  | HTML iconHTML  

    In this paper, a low-power Hamming distance associative processor employing time-domain techniques has been developed focusing on the implementation of an r-th nearest-match location identification function. The architecture not only inherits advantages of analog implementations on power consumption but also improves the accuracy of such implementations. This is because it employs digital technique for distance comparison and delay-time technique for searching for the r-th nearest-match template word. A 64-bit 32-word proof-of-concept chip has been designed and fabricated in a 0.18-¿m CMOS process and has been successfully tested. Power consumption is below 1.8 mW and core size is 0.65 × 0.445 mm2, respectively. View full abstract»

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  • Energy-aware Filter Cache Architecture for Multicore Processors

    Page(s): 58 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    Energy consumption as well as performance should be considered when designing high-performance multicore processors. The energy consumed in the instruction cache accounts for a significant portion of total processor energy consumption. Therefore, energy-aware instruction cache design techniques are essential for high-performance multicore processors. In this paper, we propose new instruction cache architecture, which is based on the level-0 cache composed of filter cache and victim cache together, for multicore processors. The proposed architecture reduces the energy consumption in the instruction cache by reducing the number of accesses to the level-1 instruction cache. We evaluate the proposed design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed technique reduces the energy consumption in the instruction cache by up to 3.4% compared to the conventional filter cache architecture. Moreover, the proposed architecture shows better performance over the conventional filter cache architecture. View full abstract»

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  • Independent Component Analysis Applied to Watermark Extraction and its Implemented Model on FPGAs

    Page(s): 71 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB) |  | HTML iconHTML  

    Most of published audio watermark algorithms are suffered a trade-off between inaudibility and detectibility, and the detection performance depends greatly on the strength of noise added by communication channels. This work introduces an audio watermarking method that can overcome this challenge, i.e. allows increasing watermark strength while preserving inaudibility. The scheme uses psychoacoustic masking compatible to MPEG layer 1 Model 1 and adjusts it in a data adaptive way. A blind watermark extraction technique using the Independent Component Analysis (ICA) is shown to minimize the watermark decoding error. An implementation of a simple quantization-based watermarking algorithm (LSB) on the Spartan-3 FPGA Starter Kit of Xilinx is also presented as a part of hardware demonstration of the method. View full abstract»

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  • Algorithm Transformation for FPGA Implementation

    Page(s): 77 - 81
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by porting them to an FPGA based hardware implementation. Porting does not always result in efficient architectures as the original algorithms are usually developed and optimized to run on a serial processor. To obtain an efficient hardware architecture, one that makes use of the available parallelism, the algorithms need to be transformed. Eleven such transformations are identified and explained. While some of these are straightforward, and have been implemented by some compilers, many cannot be automated because they require detailed knowledge of the algorithm. View full abstract»

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  • Designing a Harware Accelerator for Face Recognition Using Vector Quantization and Principal Component Analysis as a Component of SoPC

    Page(s): 82 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (458 KB) |  | HTML iconHTML  

    A flexible hardware accelerator for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real- time image compression and recognition applications. In the system, the number of elements for each codeword and the number of codewords in the system can be changed easily for different applications with the use of an embedded CPU. The architecture allows using look up tables (LUTs), single-instruction multiple data (SIMD) and two-stage pipeline architecture. This leads to high speed operation suitable for real-time applications. On the other hand, over the last ten years or so, face recognition has become a popular area of research in computer vision and one of the most successful applications of image analysis and understanding. A number of statistical analysis methods have showed their efficiencies in recognition applications. Thus, in this research, an improved method for face recognition using principal component analysis (PCA) and vector quantization (VQ) have been developed as a component of SoPC using a DSP FPGA Development Kit, Stratix II Edition from Altera. View full abstract»

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  • Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis

    Page(s): 87 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (397 KB) |  | HTML iconHTML  

    A novel high-level synthesis (HLS) technique to improve the clock frequency is presented. Our technique aims at the reduction of the clock period by eliminating interconnections, specifically multiplexers (MUXs). MUXs are generally inserted before shared functional units and shared registers. However, MUXs are also inserted before a register even if the register is not shared by multiple variables at all. This paper proposes aggressive register unsharing to remove these MUXs and to improve the clock frequency. Our proposed technique employs static single assignment (SSA) transformation, which is mainly used as a compiler intermediate representation, to behavioral descriptions. This technique is widely applicable to a variety of HLS tools because it is completely independent of the HLS tools. We have developed a complete synthesis framework using an open source compiler, COINS, for SSA transformation, a commercial HLS tool, and an in-house converter which refines a COINS-generated code into one compatible with the HLS tool. Six sets of experiments showed the clock frequency improvement by up to 61.5% and on average 26.7% with the acceptable overhead on the circuit area by on average 10.6%. View full abstract»

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  • 16-QAM Transmitter and Receiver Design Based on FPGA

    Page(s): 95 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (703 KB) |  | HTML iconHTML  

    The FPGA technology has been playing a considerable role in portable and mobile communication. This is due to the features of flexibility, accuracy and configurability in designing and implementation. The paper presents a complete design for a 16-QAM transmitter and receiver based on the Virtex4 FPGA Kit. The implemented system can be applied in particle. Based on the principles of carrier synchronization, time synchronization, core tools for phase-different detecting as well as adaptive equalization processing in System Generator (a software of Xilinx), the authors have designed a complete baseband IF 16-QAM system, in which the baseband signal is upconverted into IF frequency (up to 12MHz) at the transmitter and then is downconverted at the receiver. After timing synchronizing, the adaptive equalizing and phase recovering, the received baseband signal is displayed in the oscilloscope's screen. These accurate experiments conducted in Virtex 4 FPGA board kit have shown a promising foundation for developing coding, algorithms in 16-QAM modulation scheme. View full abstract»

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  • A More Precise Model of Noise Based PCMOS Errors

    Page(s): 99 - 102
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (375 KB) |  | HTML iconHTML  

    In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder. Our contribution helps account for the filtering effect seen in noise based PCMOS in a novel way. The characterization proposed here can enable accurate multi-bit models based on fast mathematical extrapolation instead of expensive and slow HSPICE simulations. View full abstract»

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  • A Smart CMOS Image Sensor with On-chip Hot Pixel Correcting Readout Circuit for Biomedical Applications

    Page(s): 103 - 107
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (518 KB) |  | HTML iconHTML  

    One of the most recent and exciting applications for CMOS image sensors is in the biomedical field. In such applications, these sensors often operate in harsh environments (high intensity, high pressure, long time exposure), which increase the probability for the occurrence of hot pixel defects over their lifetime. This paper presents a novel smart CMOS image sensor integrating hot pixel correcting readout circuit to preserve the quality of the captured images. With this approach, no extra non-volatile memory is required in the sensor device to store the locations of the hot pixels. In addition, the reliability of the sensor is ensured by maintaining a real-time detection of hot pixels during image capture. View full abstract»

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