Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Solid State Device Research Conference, 1987. ESSDERC '87. 17th European

Date 14-17 Sept. 1987

Filter Results

Displaying Results 1 - 25 of 231
  • 17th European Solid State Device Research Conference

    Publication Year: 1987 , Page(s): i
    Save to Project icon | PDF file iconPDF (146 KB)  
    Freely Available from IEEE
  • A Short History of the University of Bologna

    Publication Year: 1987 , Page(s): ii
    Save to Project icon | Request Permissions | PDF file iconPDF (259 KB)  
    Freely Available from IEEE
  • Welcome to ESSDERC '87

    Publication Year: 1987 , Page(s): iii
    Save to Project icon | Request Permissions | PDF file iconPDF (361 KB)  
    Freely Available from IEEE
  • [Advertisement]

    Publication Year: 1987 , Page(s): iv
    Save to Project icon | Request Permissions | PDF file iconPDF (183 KB)  
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 1987 , Page(s): v
    Save to Project icon | PDF file iconPDF (267 KB)  
    Freely Available from IEEE
  • Scientific Committee

    Publication Year: 1987 , Page(s): v
    Save to Project icon | PDF file iconPDF (267 KB)  
    Freely Available from IEEE
  • Special Sessions Organizers

    Publication Year: 1987 , Page(s): v
    Save to Project icon | Request Permissions | PDF file iconPDF (267 KB)  
    Freely Available from IEEE
  • Program

    Publication Year: 1987 , Page(s): vi - vii
    Save to Project icon | PDF file iconPDF (691 KB)  
    Freely Available from IEEE
  • Technical Program Contents

    Publication Year: 1987 , Page(s): ix - xxxviii
    Save to Project icon | PDF file iconPDF (6813 KB)  
    Freely Available from IEEE
  • BI(C)MOS Dream or Nightmare?

    Publication Year: 1987 , Page(s): 1 - 8
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1908 KB)  

    The paper presents a summary of advantages of mixed bipolar-CMOS processes for analog and digital VLSI and some design considerations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New Developements in Solid-State Detectors

    Publication Year: 1987 , Page(s): 9 - 21
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (6455 KB)  

    The interest in semiconductor radiation detectors for energy and position measurements is rapidly increasing in the fields of high energy physics, astronomy, space applications and medicine. After a brief review of the field, the recent developements are here presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Usefulness of Advanced Drain Structures as Emitters in Scaled BICMOS

    Publication Year: 1987 , Page(s): 25 - 28
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (999 KB)  

    Bipolar transistors can be implemented in a CMOS technology without excessive expense using the n-channel source/drain implantation simultaneously for the formation of the bipolar emitter. During MOS scaling the change of the drain structures from phosphorus to DID and LDD influences the individual bipolar device parameters. However this BICMOS concept can be extended to sub-¿m CMOS without loosing performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 1.2μm Bi-CMOS Technology with High Performance ECL

    Publication Year: 1987 , Page(s): 29 - 32
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1377 KB)  

    1.2μm Bi-CMOS technology with ECL gate for high speed device has been developed. A process is carefully optimized for obtaining the best performance of ECL gate without degrading 1.2μm Bi-CMOS performance and mass productivity. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multipower BCD 250V: A Versatile Technology to Realize High Performance PICs

    Publication Year: 1987 , Page(s): 33 - 36
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1013 KB)  

    The feasibility of a 250V process, named Multipower BCD, integrating Bipolar, CMOS and H. V. P-channel signal devices with DMOS power stages is demonstrated. The adopted integration scheme allows wide flexibility in the electrical output configuration. The process and device key features are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Rapid Thermal Processing of Polysilicon Emitter Bipolar Transistors in a Combined CMOS/Bipolar Process

    Publication Year: 1987 , Page(s): 37 - 39
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (817 KB)  

    The effect of RTA time on the emitter profiles and base current of polysilicon emitter bipolar transistors has been studied. Experimental results show increasing base current with anneal time. The contact saturation current density Jos has been extracted for a device with polysilicon doping level of 3×1020 cm¿3 and a 45 second 1100°C RTA. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Substrate Influences on the Activation of Ion-Implanted Si in GaAs

    Publication Year: 1987 , Page(s): 43 - 46
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2516 KB)  

    The influence of substrate material on Si-implanted CV-profiles is demonstrated on s.i. LEC grown GaAs. Local activation is affected by stoichiometry variations near dislocations. For higher concentrations the variations increase due to saturation effects. By co-implantation of As and enhanced implantation damage the activation is decreased and the dislocation influence increased. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comparison of Rapid Annealing and Furnace Annealing of Si Implanted into GaInAs

    Publication Year: 1987 , Page(s): 47 - 50
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1033 KB)  

    The activation efficiency of conventionell furnace annealing (650°C-900°=C, 30 min, SiO2 cap, N2 ambient) and rapid thermal annealing (600°C-900°C, with and without SiO2 cap, N2 ambient) has been compared in Si doped GaInAs layers grown lattice matched by either OMVPE or LPE on InP. Carrier profiles and atomic profiles have been determined by selective Hall measurement, C/V profiling and SIMS measurements. For an implantation dose of 2*1014 cm¿2 and rapid thermal annealing at 900 °C activation of 69 % with a sheet resistance of 20 ¿ is found. Rapid thermal annealing and furnace annealing lead to comparable activation efficiency and Hall mobility data. A broadening of carrier concentration profile for furnace annealing at 700°C, 30 min is observed. Rapid thermal annealing between 700°C and 900°C leads to no measurable change in Si profile. In case of low dose Si implantation in OMVPE grown layers highest activation (65 %) is achieved for rapid thermal annealing at 700°C. The electron mobility at a doping concentration of 1017 cm¿3 is 5800 cm2V-1s¿1. For low dose Si implantation in LPE grown layers the activation is 100% after rapid annealing at 800°C. Long furnace annealing (700°C, 30 min ) results in an anomalous high carrier concentration at the surface. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Yield-Performance Considerations for Ion-Implanted GaAs Integrated Circuits based on Substrate Material Properties

    Publication Year: 1987 , Page(s): 51 - 54
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2133 KB)  

    In this article we will illustrate, in terms of yield-performance considerations, how for conventional annealing techniques the doped LEC materials (i.e. lightly Cr or In-doped) prove to be better than the undoped material, primarly because of the higher yield capability, and that before full advantage can be taken from the potentially better undoped material then either an improved annealing technique and/or ingot annealed material must be considered. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Novel 1500 Volt IGBT Device with Improved Turn-Off Performance

    Publication Year: 1987 , Page(s): 57 - 59
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1021 KB)  

    An Insulated Gate Bipolar Transistor design based on bulk silicon material capable of blocking voltages in excess of 1500V is reported. The device incorporates a detailed anode shorting pattern which inhibits hole injection during on-state, and reduces turn-off times. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of a 1600 V Power Bipolar Mode FET (BMFET)

    Publication Year: 1987 , Page(s): 61 - 64
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2211 KB)  

    The design, the fabrication and the characterization of a BMFET (Bipolar Mode FET) with a maximum voltage of 1600 V and maximum current of 5 A (at hFS = 2.5) are reported. With the help of theoretical models, the effects of physical and geometrical parameters on the performance of the device are investigated and the rules to be used in the design are defined. The switching characteristics of the fabricated devices show that the BMFET gives full Reverse Safe Operating Area and fall-time down to 30 ns on inductive load. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modelling Bipolar Transistor Second Breakdown During Turn-Off by Solution of the Fundamental Device Equations

    Publication Year: 1987 , Page(s): 65 - 69
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1301 KB)  

    Numerical simulations have been made of the turn-off of two-dimensional power bipolar transistor structures, under inductive loading, by alternate solution of the fundamental device equations and the circuit equations at each time step. The results have shown that current spreading reduces the magnitude of the electric field in the collector produced by the space charge of mobile electrons, so leading to improved reverse bias second breakdown performance. Removal of the central portion of the emitter effectively increases the current spreading and gives a further reduction in the space charge induced field. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Processing and Characterization of Ultra-Small Silicon Devices

    Publication Year: 1987 , Page(s): 71 - 80
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (4104 KB)  

    Processing, design, and characterization issues are discussed for advanced field-effect (FET) and bipolar transistors. Results are presented from work on N-channel FET's with gate lengths below 0.1 ¿m, and on the role that polysilicon emitter contacts play in high current, high speed bipolar devices. For FET's over 750mS/mm transconductance was achieved at liquid nitrogen temperature operation. In the case of bipolar devices it was found that maximizing the gain enhancement derived from the polycrystalline/single-crystal interface without regard to resistive effects does not lead to the highest performance in submicron transistors. Based on previous experience and on our recent work, we believe that silicon technology faces no insurmountable obstacles as it progresses into the deeply submicron regime. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Half Micrometer N-MOS Technology Using X-Ray Lithography

    Publication Year: 1987 , Page(s): 83 - 86
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1717 KB)  

    MOSFETs with effective channel lengths down to 0.3 ¿=m have been realized using x-ray lithography. To determine process parameters for device optimization two dimensional process and device modeling was employed. In addition, ring oscillators with different numbers of stages were fabricated to evaluate the performance of this technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Offset Diffused Drain Transistors for Half-Micron CMOS

    Publication Year: 1987 , Page(s): 87 - 90
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1175 KB)  

    Half-micron n- and p-channel transistors with an offset diffused drain structure have been fabricated. A high temperature process and offset implantation of the source-drain dopants was used to obtain graded doping profiles and an optimum effective channel length. Experimental results showed good device quality. The extrapolated lifetime for the n-channel device was 5 years at a power supply voltage of 4.5 V. Hot carrier degradation in p-channel devices cannot be neglected anymore. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 0.5 μm CMOS Device Design and Characterization

    Publication Year: 1987 , Page(s): 91 - 94
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1305 KB)  

    The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n+ polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned titanium silicides. To control channel hot electron degradation effects in the NFET device with 3.3V power supply, different S/D junctions with graded profiles are investigated. The n-well doping profile is adjusted to provide adequate short channel threshold control and punch-through immunity in the buried channel PFET. In this paper, measured device characteristics will be discussed. Stage delays of unloaded inverter ring oscillators down to 90 pS are presented. Circuit performance sensitivities to a variety of parameters such as channel length. power supply and series resistance are also shown. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.