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Embedded and Multimedia Computing, 2009. EM-Com 2009. 4th International Conference on

Date 10-12 Dec. 2009

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  • EM-Com 2009 - Title page

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  • EM-Com 2009 [Copyright notice]

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  • EM-Com 2009 Message from the General Chairs

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  • EM-Com 2009 Message from the Program Chairs

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  • EM-Com 2009 Organization

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  • UMCC 2009 Welcome Message

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  • EM-Com 2009 List of Papers

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  • EM-Com 2009 author list

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  • A Framework for Stream Programming on DSP

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (210 KB) |  | HTML iconHTML  

    There has recently been much interest in stream processing, both in industry (Cell, Storm series, NVIDIA G80, AMD FIRESTREAM) and academia (IMAGINE). Some researchers have accelerated a lot of applications in media processing, scientific computing and signal processing with a special programming style called stream programming. This paper presents a framework to program DSP with this special programming style. Stream program can run on DSP without any architectural support. H264 encoding is selected to evaluate our technique. The result shows that significant speedup is achieved, ranging from 3.2x for cavlc up to 7.1x for analysis. View full abstract»

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  • High Speed USB 2.0 Interface for FPGA Based Embedded Systems

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (751 KB) |  | HTML iconHTML  

    FPGA implementation of high speed serial peripherals such as USB 2.0 are of great use. The Cypress SX2 USB 2.0 controller is one of the suitable choices for developing FPGA based USB peripherals. A simple interface module capable of transferring data rates above 400 Mbits/s can be implemented to communicate with SX2. FPGAs can efficiently be used for building embedded systems. Xilinx complete set of development tools make implementation of large system-on-chip designs feasible. We present two complete architectures for connecting SX2 to FPGA. First design minimizes FPGA resource usage while keeping a reasonable speed. In the second design, optimizations are done to reach maximum USB 2.0 interface speed at the cost of some additional logic. In order to use developed module in Xilinx embedded design flow, we make a custom peripheral which includes SX2 interface as its core and additional logic capable of connecting to OPB and PLB. View full abstract»

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  • Embedded Data Fusion Toolbox: A Model Driven Architecture

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB) |  | HTML iconHTML  

    Reducing time to market, design cost and fast developing, prototyping and testing of embedded industrial and automation models are very interesting topics in recent manufacturing and industry methodologies. In recent years, Model driven architecture or engineering methodology has been introduced in the field of software engineering by OMG. This methodology separate platform independent, and platform specific concerns, and could be utilized and extended to other fields of engineering. In many industrial applications, embedded, distributed and fast sensory data fusion operators are necessary, and system complexities could be dominated by low level dedicated fast fusion operators on real time hardware platforms such as CPLDs and FPGAs. In this experience, embedded data fusion toolbox has been developed for fast design, prototyping, test and implementation of simple fusion operators on embedded industrial platforms. This toolbox has been implemented in MATLAB/Simulink environment via behavioral arithmetic to the implementation on either FPGA. Reusability, scalability, chip area, precision and other design criteria are considered in design process, and desired HDL models could be obtained automatically. This fully automated toolbox is extendible for complex data fusion operators, subsequently the platform-independent model can be translated to a platform-specific model (PSM) by mapping the PIM to some implementation language or platform using formal rules in order to preparing targeted models in different platforms. View full abstract»

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  • Implicit Data Permutation for SIMD Devices

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (203 KB) |  | HTML iconHTML  

    SIMD extension is one of the most effective ways to exploit data level parallelism in current microprocessor design. But limited by some constraints, such as memory address alignment and in consecutive memory access, data permutation operations are usually needed before SIMD calculations, which impede us to exploit more parallelism. In this paper, an implicit data permutation mechanism is proposed. With our approach, original explicit data permutation can be split into two stages: explicit pattern setting and implicit data reorganization. The first stage is performed by scalar instructions and the second one is triggered implicitly when a vector register is read. It provides new chance for further optimization. To make this mechanism programmable, several new scalar instructions are extended and corresponding compilation strategies are also proposed. Experimental results show that oriented to multimedia benchmarks, 1.18x speedup can be achieved over current SIMD optimization techniques on average. View full abstract»

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  • A Entropy Decoding Design for High Definition Video in H.264 Baseline Profile

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    In this paper, a real-time entropy decoder for HD video is designed, the whole decoding process is controlled under a finite state machine and the codeword is divided into three parts such as SPS/PPS/SliceHeader, CAVLC and EXP-Golomb. Due to variable length code, the five syntax elements of CAVLC will be parsed step by step. In the proposed implementation, a look-up table algorithm based on pos (the number of zero) is exploited and may be divided into sub-table according to priority in the same pos. The synthesis results show that the architecture can satisfy the requirement for a 1920×1080p@30fps high definition decoding. View full abstract»

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  • Hierarchical Loop Partitioning For Rapid Generation of Runtime Configurations

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (309 KB) |  | HTML iconHTML  

    Runtime reconfiguration provides an efficient means to reduce the hardware cost, while satisfying the performance, flexibility and power requirements of embedded systems. The growing complexity of the applications necessitates methods that can rapidly identify a suitable set of configurations by splitting the computational structures into temporal partitions in order to evaluate the benefits of runtime reconfiguration early in the design cycle. In this paper, we present a hierarchical loop partitioning strategy that reduces the complexity of the search space for determining the runtime custom instruction configurations for reconfigurable processors. Experimental results show that the proposed partitioning strategy can lead to an average and maximum performance gain of over 14% and 31% respectively when compared to a recently reported technique. In addition, when compared to the existing technique, the proposed partitioning method has significantly lower runtime in many of the cases considered. View full abstract»

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  • PRESSNoC: Power-Aware and Reliable Encoding Schemes Supported Reconfigurable Network-on-Chip Architecture

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1376 KB) |  | HTML iconHTML  

    We propose a Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) architecture whereby an encoding can be selected by a REasoning And Learning (REAL) framework at run-time to fit the reliability and power requirements of the application and its execution environment. PRESSNoC was implemented on a Xilinx Virtex 4 FPGA device, which required 25.5% lesser number of slices compared to the traditional NoC with a full-fledged encoding method. The average benefit to overhead ratio of the proposed architecture is greater than that of the traditional architecture by 71%, 32%, and 277% when we consider the individual effects of interference rate per instruction, application domains, and system characteristics, respectively. It shows we have higher probability toward the reduction of crosstalk interferences and dynamic power consumption at the same overheads by using the proposed architecture. View full abstract»

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  • A Framework for the Correction of Multi-Bit Errors in Multi-Core Processors

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    With the development of the scaling technologies, it's more susceptible to the transient faults for the modern microprocessors, so the error-correcting codes are used to detect and correct the errors in caches. In this paper, an enhanced architecture is proposed for the selective use of strong multi-bit ECC, where the main character is the extended L2 core, protected by Hamming distance to detect errors, and carried some redundancy-based schemes to correct errors. To the detailed design of the cache, these schemes includes the L1/L2 cache redundancy, fine grain dirtiness, reliability-centric replacement and the methods to exploit small data value size. View full abstract»

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  • Use Object-Oriented Platform to Facilitate FPGA-Based Computing in Embedded Systems

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (129 KB) |  | HTML iconHTML  

    As a special-purpose computer system to solve specific problems, the embedded system is very suited to be implemented by the FPGA. However, without fixed hardware architecture, the FPGA-based computing system is mostly a mixture of hardware and software. This kind of system is difficult to design because hardware and software are developed using quite different models of computation. To handle this problem, a FPGA-based platform supporting Java programming language is proposed in this paper. This platform has two aspects: 1) to find the applications amenable to very large speedup using FPGA-based systems, such as computer vision, image processing, microarray analysis and so on. 2) To provide a three level solution making the hardware transparent to application programmers. This platform is expected to provide an effective way to accelerate FPGA-based custom computing to be used in embedded systems. View full abstract»

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  • A Model-Based Soft Errors Risks Minimization Approach

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (241 KB) |  | HTML iconHTML  

    Minimizing the risk of system failure in any computer structure requires identifying those components whose failure is likely to impact on system functionality. Clearly, the degree of protection or prevention required against faults is not the same for all components. Tolerating soft errors can be much improved if critical components can be identified at an early design phase and measures are taken to lower their criticalities at that stage. This improvement is achieved by presenting a criticality ranking (among the components) formed by combining a prediction of faults, consequences of them, and a propagation of errors at the system modeling phase; and pointing out ways to apply changes in the model to minimize the risk of degradation of desired functionalities. Case study results are given to validate the approach. View full abstract»

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  • On the Handling Node Failure: Energy-Efficient Job Allocation Algorithm for Real-Time Sensor Networks

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    Guaranteeing quality of real-time services in wireless sensor networks (WSN) requires efficient resource management, especially for energy resources. This is due to the fact that nodes in such networks usually use limited non-replaceable batteries. On the other hand, the nodes of WSNs often work in harsh environments, and therefore, susceptible to failure occurrences due to environmental affects or exhaustion of their battery. In this paper, we present a dynamic energy efficient real-time job allocation algorithm called ERTJA for handling node failures in a cluster. ERTJA tries to minimize the energy consumption of the cluster by minimum activation of sleeping nodes while guaranteeing the QoS of the application assigned to the cluster at the same previous level. Further, when the number of sleeping nodes is limited, the proposed algorithm uses the idle times of active nodes to have a graceful QoS degradation of the cluster upon node failure. Simulation results show significant performance improvements of ERTJA in terms of energy consumption comparing to the N-EDF-Plus algorithm. According to the results, ERTJA can save up to 26.5% of the cluster's energy consumption with respect to N-EDF-Plus in the studied scenarios. View full abstract»

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  • Optimizations for ARM11 MPCore on Computational Capabilities and Interrupt Processing

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    In this contribution, several optimization strategies for fully exploiting the performance of ARM11 MPcore have been discussed. Experimental studies are conducted for the basic computation performance and the multimedia processing performance of ARM11 MPcore. The basic computation operation includes integer operation and floating-point operation. Results show that an efficiency gain of a factor 3.8 for integer operation could be achieved when being optimized by using the OpenMP parallel computing model, and for floating-point operation, the value is 3 to 5 when adopting the VFP (vector float point) optimization method. With regard to the multimedia processing, two optimization methods are put forward, namely, the DCT optimization with VFP and the parallelization of audio decoding, video decoding and playing. The experimental results show that both methods could efficiently improve the performance of multimedia processing for ARM11 MPCore. In addition, considering that the interrupt load imbalance on multicore processor may bottleneck the entire system's performance improvement, workload balancing methods basing on interrupt affinity are proposed for ARM11 MPcore, and results indicate these methods are effective. View full abstract»

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  • TMS: Visual Monitoring of Trusted Platform Board for Trust Computing Based on Web

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (530 KB) |  | HTML iconHTML  

    The TPB (trusted platform board) is an expansion of the TPM (trust platform module) chip for the elevation of the efficiency and usability of the TPM chip that has been developed from the TCG (trusted computing group) for the trust computing. In addition to the TPB function supporting environments for the high-standard trust within the hardware standard of the system, the present paper develops the TMS (trust monitoring system) that provides the visualization of the real-time monitoring for the system resources (process, memory, network, users, etc.). Moreover, TMS is not only the Internet-based computing environment for the system resources but also the real-time monitoring system for the cloud computing environment. View full abstract»

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  • Smartcard-Based Secret Sharing for Secure Fingerprint Verification

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (195 KB) |  | HTML iconHTML  

    Recently, in the smartcard-based authentication system, there is an increasing trend of using fingerprint for the card holder verification, instead of passwords. However, the security of the fingerprint data is particularly important as the possible compromise of the data will be permanent. To protect the fingerprint data, techniques such as "fuzzy vault" which is based on the difficulty of the polynomial reconstruction need to be developed for the smartcard-based environment. In this paper, we propose a secure and efficient approach which reconstructs a polynomial on a smartcard with the aid of a server by using fuzzy fingerprint vault distributed into the smartcard and the server. Based on the experimental results, we confirmed that our secret sharingbased approach can perform the fuzzy vault-based fingerprint verification more securely (by a factor of'300) and quickly (by a factor of 17) on a combination of a smartcard and a server. View full abstract»

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  • An Automatic RFID and Wireless Sensing System on a GHS-Based Hazardous Chemicals Management Platform

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (370 KB) |  | HTML iconHTML  

    A RFID and wireless sensing network have been developed to improve a GHS-based intelligent management platform deployed on campus, which monitors the hazardous chemicals inventory at a number of laboratories. The developed RFID and wireless sensing system can automatically update the inventory of monitored chemicals periodically or respond the server's request instantly to check the usage and storage of the chemicals so that ignorance or misconduct of laboratory operators can be prevented or detected shortly to assure the safety of campus. Unlike the traditional RFID inventory control system, even the little quantity change in the chemical container can be detected and recorded to enhance the inventory control with the innovation of this system. This automatic system can be deployed and transmit data wirelessly in laboratories to minimize the cost and complexity of implementation. It also can communicate with the remote GHS-based management server via internet such that administration can oversee all the inventory of chemicals in the laboratories with this system installed. The implementation of this system has shown its effectiveness to improve the safety and accuracy of inventory control of the toxic chemicals on campus. View full abstract»

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  • A TPN Based Framework for the Specification of Real Time Embedded Systems

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    We propose in this paper a new modular framework to specify real time embedded systems. This model allows to express the behavior of a system through a specification that composes time Petri nets with algebraic operators. We provide its formal semantics and show how it can be used to capture the behavior of many complex real time systems. View full abstract»

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  • Power-Aware Mapping for Network-on-Chip Architectures under Bandwidth and Latency Constraints

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (301 KB) |  | HTML iconHTML  

    This paper investigates the bandwidth- and latencyconstrained IP mapping problem that maps a given set of IP cores onto the tiles of a mesh-based Network-on-Chip (NoC) architecture to minimize the power consumption due to intercore communications. By examining various applications' communication characteristics shown in their communication trace graphs, two distinguishable connectivity templates are realized: the graphs with tightly coupled vertices and those with distributed vertices. Different mapping heuristics are developed for these templates: tightly coupled vertices are mapped onto tiles that are close to each other while the distributed vertices are mapped following a graph partition scheme. The proposed template-based mapping algorithm achieves on average 15% power saving compared with MOCA, a fast greedy-based algorithm. Compared with a branch-and-bound algorithm, the proposed algorithm can generate results of almost the same quality but require much less CPU time. View full abstract»

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