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# Proceedings of the 2009 12th International Symposium on Integrated Circuits

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Displaying Results 1 - 25 of 175
• ### [Title page]

Publication Year: 2009, Page(s):1 - 2
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• ### Low power current mode pipelined A/D converter with 2.5-bit/stage and digital correction

Publication Year: 2009, Page(s):1 - 4
Cited by:  Papers (1)
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This paper presents a novel prototype low power current mode 9-bit pipelined A/D converter. The A/D converter structure is composed of three 2.5-bit and one 3 bit stages operating in current mode and final comparator which converts the analog current signal into digital voltage signal. All building blocks of the converter have been designed in CMOS AMS 0.35 ¿¿m technology, then simulated, fabricat... View full abstract»

• ### A high-resolution time-interleaved delta-sigma modulator with low oversampling

Publication Year: 2009, Page(s):5 - 8
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This paper proposes a new two-channel time-interleaved delta-sigma modulator (DSM). The time-interleaved approach can reduce four times of sampling rate as compared with the conventional delta-sigma modulator and the performance is much better. This technique can relax the limitation of high-gain and high-speed requirements of opamps in the DSM design and thus it can reduce the design complexity a... View full abstract»

• ### Stability analysis and system design of sigma-delta modulators

Publication Year: 2009, Page(s):9 - 12
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A system design with new empirical stability criteria for sigma-delta modulators is proposed. The stability criteria is a cubic function obtained by the least square method, and simulations including coefficients variation due to component mismatches of circuit implementation are included. By using the proposed methodology, several stability criteria of different targets (e.g., architectures, over... View full abstract»

• ### A low-power wide-range interface circuit for nanowire sensor array based on resistance-to-frequency conversion technique

Publication Year: 2009, Page(s):13 - 16
Cited by:  Papers (2)
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A traditional oscillator approach which implements the resistance-to-frequency conversion is shown to be effectively used as interface circuit for nanowire sensor array. The interface readout circuit is configurable in terms of output frequency and achieves a highly linear detection range over sensor resistance of 1 MÂ¿ to 1 GÂ¿ without any calibration system. A three-bit digitally-controlled curr... View full abstract»

• ### Characterization and implementation of nonlinear logic cell models for analog circuit simulation

Publication Year: 2009, Page(s):97 - 100
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During back-end verification of digital circuits, analog circuit simulation is an indispensable, but time consuming, process. To reduce simulation time, current source models (CSMs) have been proposed to replace transistor netlists of logic cells. In this paper, physically motivated requirements for accurate CSMs are derived. By employing the topological information of the netlist, very short char... View full abstract»

• ### K-locked-loop and its application in time mode ADC

Publication Year: 2009, Page(s):101 - 104
Cited by:  Papers (3)
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VCO is commonly used in time mode ADC to convert analog input voltage to time/phase information, where the time/phase information is subsequently converted to digital code using time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inherent nonlinear property of VCO however has become the bottle neck for time mode ADC. In this paper,... View full abstract»

• ### Saving potentials of Adiab. Logic on system level: A CORDIC-based adiabatic DCT

Publication Year: 2009, Page(s):105 - 108
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The energy consumption of digital systems can be greatly reduced by applying adiabatic logic (AL). Making best use of AL requires a dedicated system design regarding the inherent characteristics of AL. In this paper we investigate the CORDIC architecture, that can be used for various signal processing algorithms and is preeminently suitable for AL. For fast functional testing, we propose a methodo... View full abstract»

• ### A circuit based behavioral modeling of Continuous-Time Sigma Delta modulators

Publication Year: 2009, Page(s):109 - 112
Cited by:  Papers (2)
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In evaluating continuous-time sigma delta (Â¿Â¿) modulators, the generation of highly accurate results requires long simulation time due to the nonlinear nature of the system. In most cases, a compromise has to be made to trade off precision for speed. This paper presents a circuit-based high level model implemented in the MATLAB SIMULINK environment so as to achieve a faster speed of simulation. ... View full abstract»

• ### RaGAzi: A random and gradient-based approach to analog sizing for mixed discrete and continuous parameters

Publication Year: 2009, Page(s):113 - 116
Cited by:  Papers (1)
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Sizing of analog circuits requires the consideration of both continuous and discrete design parameters, e.g. due to predefined manufacturing grids. In this paper, a new method is presented to solve this task. It is based on an iterative optimization process with random-based searches on search regions that are determined by performance gradients. Experimental simulation results of operational ampl... View full abstract»

• ### Tradeoff of energy and hardware resources in high level synthesis

Publication Year: 2009, Page(s):117 - 120
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This paper studies the energy consumed in VLSI systems that have multiple-stage functionally pipelined datapath. A two-process approach is then proposed to synthesize such datapath by partitioning the datapath into multiple pipelined stages that can be operated with multiple frequencies and multiple supply voltages, aiming to reduce energy consumed by the datapath. Experimental results show that t... View full abstract»

• ### Analog circuits for physical cryptography

Publication Year: 2009, Page(s):121 - 124
Cited by:  Papers (2)
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This paper presents circuit designs to be used as public-key' physical uncloneable functions. We will introduce two specially designed circuits: skew' memories and massively parallel analog processor arrays (CNNs). We show that such circuits-which are possible to simulate but computationally outperform any feasible digital and hardware-assisted emulation-can be used to remotely and securely iden... View full abstract»

• ### Impact of CNT arrangement on capacitance and inductance in mixed bundles

Publication Year: 2009, Page(s):236 - 239
Cited by:  Papers (1)
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Increasing limitations of copper interconnect with technology scaling drives us to look for new wiring solutions in high performance IC design. Carbon nanotubes (CNTs) are promising candidates to address this challenge. Here the possibility of using a rearranged mixed bundle structure consisting of single wall carbon nanotubes (SWCNT) and multi wall carbon nanotubes (MWCNT) has been explored. SWCN... View full abstract»

• ### High efficiency carbon nanotube based solar cells for electronics devices

Publication Year: 2009, Page(s):240 - 243
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Due to the increasing energy needs and the demand for green source of energy, there has been a surge of interest in finding solutions for crossing the efficiency barriers of solar cells. Ranging from traditional Si-based solar cells, dye-sensitized solar cells (DSSC) and other organic cells have a theoretical limit on the efficiency of 30%. This paper provides an in-depth exposure to the new techn... View full abstract»

• ### Low-power and robust six-FinFET memory cell using selective gate-drain/source overlap engineering

Publication Year: 2009, Page(s):244 - 247
Cited by:  Papers (4)
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A new FinFET memory circuit technique based on gate-drain/source overlap engineering is proposed in this paper. The read stability of the proposed SRAM circuit is enhanced by 53% and the leakage power is reduced by 48% as compared to a minimum sized low-threshold-voltage FinFET SRAM cell in a 32 nm FinFET technology. Furthermore, the layout area of the proposed SRAM circuit is reduced by 17% as co... View full abstract»

• ### Exploiting SWCNT structural variability towards the development of a photovoltaic device

Publication Year: 2009, Page(s):248 - 251
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In this paper we propose a conceptual Photovoltaic device that comprises a large number of vertically aligned single-walled carbon nanotubes (SWCNT) having distinct geometrical structure properties. Through employing analytical models of the CNT, we demonstrate how this structural variation can be exploited in absorbing a broadband of the solar spectra. The results show that given a group of CNTs ... View full abstract»

• ### Effect of variability in SWCNT-based logic gates

Publication Year: 2009, Page(s):252 - 255
Cited by:  Papers (3)
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This work is concerned with carbon nanotube diameter variations and the resulting uncertainties on the behavior of logic gates made from single walled carbon nanotubes (SWCNTs). Monte Carlo simulations were performed for logic gates based on CNTs of different mean diameters using the Stanford CNFET model. Delay characteristics of logic gates (NOT, NAND, NOR) are studied. This work reveals that log... View full abstract»

• ### Novel intra prediction algorithm using residual prediction for low power multimedia codecs

Publication Year: 2009, Page(s):324 - 327
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This paper proposes a novel residual prediction algorithm to improve the coding efficiency. It extends the scope of prediction to the residual data. The proposed algorithm is adopted for intra prediction which accounts for a major portion of the bit stream. The simulation results show that the proposed algorithm can reduce the bit-rate by up to 4.34% compared with the JM reference software without... View full abstract»

• ### VLSI design to unify IDCT and IQ circuit for multistandard video decoder

Publication Year: 2009, Page(s):328 - 331
Cited by:  Papers (1)
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We describe a design method to unify the IDCT and IQ operations for three popular video compression standards such as H.264 (up to high profile), MPEG-4 and VC-1. We use the concept of delta coefficient matrix to implement the unified IDCT circuit. Our circuit supports 4-point and 8-point IDCT's for H.264, MPEG-4 and VC-1. The unified IQ circuit uses a shared multiplier. The entire circuit was ver... View full abstract»

• ### Impact of process variation on timing characteristics of MTCMOS flip-flops for low-power mobile multimedia applications

Publication Year: 2009, Page(s):332 - 335
Cited by:  Papers (1)
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In mobile multimedia applications, low power is a very important requirement for hardware systems. Reducing the standby power to a negligible level, multi-threshold CMOS (MTCMOS) has been accepted as one of the most effective circuit techniques for low power design of the mobile equipments. However, the aggressive technology scaling has increased process variation, which in turn has caused signifi... View full abstract»

• ### Fast H.264/AVC motion estimation algorithm using adaptive search range

Publication Year: 2009, Page(s):336 - 339
Cited by:  Papers (2)
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With the advent of new video standards such as H.264/AVC, the demands for low-complexity advanced video coding (AVC), particularly for the subfunction of variable block searching motion estimation, is increasingly important for efficient system designs. The motion estimation needs heavy computations and many external memory accesses which are the main sources of the system complexity and power con... View full abstract»

• ### Dynamic range compression algorithm for mobile display devices using average luminance values

Publication Year: 2009, Page(s):340 - 343
Cited by:  Patents (4)
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This paper presents a dynamic range compression method for improving the contrast of color images. A variable transformation is applied to the input image, depending on the local dependency of the intensity. In this work, we present a local contrast correction algorithm that allows for simultaneous lowlight region and high-light region adjustments, based on multi-scale Gaussian filtering. Also, to... View full abstract»

• ### A CMOS low-power variable-gain amplifier with RSSI for a noncoherent low data rate IR-UWB receiver

Publication Year: 2009, Page(s):425 - 428
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A low-power variable-gain amplifier (VGA) with integrated received signal strength indicator (RSSI) for a low data-rate impulse radio ultra-wideband (IR-UWB) receiver is designed and implemented in a CMOS 0.18 Â¿m technology. The VGA achieves a gain range from -9 dB to 63 dB and bandwidth from 31 to 187 MHz. An input P1dB of -15.4 dBm is achieved at zero-dB gain. The RSSI has a dynamic range more ... View full abstract»

• ### Feedforward technique for offset cancellation in broadband differential amplifiers

Publication Year: 2009, Page(s):429 - 432
Cited by:  Papers (3)
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This paper presents a new feedforward offset cancellation technique for broadband amplifiers which are used in high speed communication systems. Unlike other conventional techniques, such as feedback cancellation or AC coupling, the proposed technique eliminates the need for larger area passive components and avoids the potential stability issue by eliminating the feedback path. Implementing in 90... View full abstract»

• ### An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power

Publication Year: 2009, Page(s):433 - 436
Cited by:  Papers (1)
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A new ultra low-power CMOS Electromyograph (EMG) amplifier is presented in this paper. It is based on the application of a novel capacitive load reduction circuit technique to the capacitive-reset switched-capacitor circuit architecture. This is achieved by adding a capacitor in series with the capacitive load of the amplifier so as to reduce the total effective load capacitance being seen by the ... View full abstract»