IEEE.org| IEEE Xplore Digital Library| IEEE Standards| IEEE Spectrum| More Sites

Cart (Loading....) | Create Account | Sign In

Author Search^beta | Advanced Search | Preferences | | More Search Options

Browse Conference Publications > Specification & Design Languag ...

Specification & Design Languages, 2009. FDL 2009. Forum on

| Create Account

IEEE Account

Change Username/Password
Update Address

Purchase Details

Payment Options
Order History
Access Purchased Documents

Profile Information

Communications Preferences
Profession and Education
Technical Interests

Need Help?

US & Canada: +1 800 678 4333
Worldwide: +1 732 981 0060
Contact & Support

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.

Please enter a valid username or password.

For Institutional Users:

More Search Options

Specification & Design Languages, 2009. FDL 2009. Forum on

Date 22-24 Sept. 2009

Quick Links

Filter Results

You have selected:

You have selected:

Title History

High level synthesis using operation properties

A re-use methodology for formal SoC protocol compliance verification

RAT-based formal verification of QDI asynchronous controllers

SMT-based stimuli generation in the SystemC Verification library

ISIS: Runtime verification of TLM platforms

Local application of simulation directed for Exhaustive Coverage of Schedulings of SystemC specifications

Exploration of embedded memories in SoCs using SystemC-based functional performance models

Design automation model for application-specific processors on reconfigurable fabric

Rapid prototyping of a DVB-SH turbo decoder using high-level-synthesis

Transaction level modeling of an adaptive multi-standard and multi-application radio communication system

Mixed simulation kernels for high performance virtual platforms

Checkpoint and Restore for SystemC models

The application of Aspectual Feature Module in the development and verification of SystemC models

Another take on functional system-level design and modeling

Efficient approximately-timed performance modeling for architectural exploration of MPSoCs

Optimizing HW/SW Co-simulation based on run-time model switching

Fast and unified SystemC AMS - HDL simulation

A VHDL-AMS modeling methodology for top-down/bottom-up design of RF systems

Design of experiments for effective pre-silicon verification of automotive electronics

A top-down approach for the design of low-power microsensor nodes for wireless sensor network

HSPICE implementation of a numerically efficient model of CNT transistor

A SystemC superset for high-level synthesis

EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applications

DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code

Proposal to extend frequency domain analysis in VHDL-AMS

IEEE Account

Purchase Details

Profile Information

Need Help?