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Specification & Design Languages, 2009. FDL 2009. Forum on

Date 22-24 Sept. 2009

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Displaying Results 1 - 25 of 37
  • High level synthesis using operation properties

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (692 KB) |  | HTML iconHTML  

    We propose a high level synthesis approach to generate RT level hardware from a specification of operation properties. The property language is called InTerval language (ITL) and we assume the set of properties is complete, such that the properties alone are strong enough to map every possible sequence of input data to exactly one sequence of output data. A major advantage of using operation properties as a design method is the existence of commercial tools to check the completeness and consistency of the property set. Furthermore, operation properties are well suited for specifications of consecutive operations of finite length. We show the practicality of our method by implementing a particle filter for a localization application. View full abstract»

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  • A re-use methodology for formal SoC protocol compliance verification

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (4647 KB) |  | HTML iconHTML  

    We propose a new methodology for formally specifying on-chip bus protocols and for verifying protocol compliance of communication blocks in System-on-Chip (SoC) designs. In this methodology, the bus protocol is specified in a design-independent way by a set of protocol compliance properties based on a generic recorder finite state transition system. The properties are verified by combining local reachability analysis with a SAT-based property checking approach. This approach is called interval property checking and is based on a bounded circuit model generated from the design and the recorder. The proposed methodology clearly differentiates between design-specific and protocol-specific aspects of the overall verification task and exploits the nature of typical SoC protocol specifications and implementations. In this way, the proposed methodology contributes to reaching two important goals: making the computational complexity of formal verification algorithms tractable for large designs and reducing the manual effort of applying formal methods in industrial practice. Our approach has been applied successfully on several industrial designs. View full abstract»

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  • RAT-based formal verification of QDI asynchronous controllers

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (641 KB) |  | HTML iconHTML  

    This paper presents a new method for formally verifying asynchronous circuits with a symbolic model checking tool called RAT. The main idea is to use a PSL description which models the circuit and gate behaviors. For each circuit, the behavior correctness is formally checked with RAT. The gates are abstracted by their PSL properties. As the gates are assembled together to build a larger circuit, the PSL properties can also be combined to describe the resulting circuit behavior. Therefore this circuit behavior can also be checked by the same method and then abstracted by PSL properties. The method can be applied hierarchically which prevents this formal verification from any explosion of the state number. In order to illustrate this technique, a case study-a QDI controller based on communicating elements called sequencers-is presented. View full abstract»

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  • SMT-based stimuli generation in the SystemC Verification library

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (340 KB) |  | HTML iconHTML  

    Modelling at the electronic system level (ESL) is the established approach of the major system-on-chip (SoC) companies. While in the past ESL design covered design methodologies only, today also verification and debugging is included. To improve the verification process, testbench automation has been introduced highlighted as constraint-based random simulation. In SystemC - the de facto standard modelling language for ESL - constraint-based random simulation is available through the SystemC verification (SCV) library. However, the underlying constraint-solver is based on binary decision diagrams (BDDs) and hence suffers from memory problems. In this paper, we propose the integration of new techniques for stimuli generation based on satisfiability modulo theories (SMT). Since SMT solvers are designed to determine a single satisfying solution only, several strategies are proposed forcing the solver to generate more than one stimuli from different parts of the search space. Experiments demonstrate the advantage of the proposed approach and the developed strategies in comparison to the original BDD-based method. View full abstract»

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  • ISIS: Runtime verification of TLM platforms

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    The context of this paper is the dynamic assertion-based verification (ABV) of TLM SystemC models. We have developed a methodology for checking temporal properties during the SystemC simulation. The assertions are expressed in the PSL language, including the possibility to use its modeling layer, and the method supports timed as well as untimed TLM descriptions. It is implemented in a prototype tool called ISIS. We describe its principles and technical characteristics, and we report various experimental results. View full abstract»

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  • Local application of simulation directed for Exhaustive Coverage of Schedulings of SystemC specifications

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (420 KB) |  | HTML iconHTML  

    The SCV library and its commercial counterparts have been effectively applied in electronic system level (ESL) for the production of test benches for system-level specifications in SystemC. Other works have enable the exploration, for fixed input data, of the different valid (fulfilling the SystemC simulation semantics) behaviours of the specification. The most efficient ones require the analysis of data and synchronization dependencies of the specification. However, in complex and heterogeneous specifications, there can be parts where such analysis becomes unfeasible. To overcome it, this paper enables and proposes the local application of simulation directed for exhaustive coverage of schedulings (or DEC simulation) for those parts. The paper shows how these features, not currently provided by any SystemC simulator, have been integrated and validated as an extension of the OSCI SystemC reference kernel. View full abstract»

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  • Exploration of embedded memories in SoCs using SystemC-based functional performance models

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (383 KB) |  | HTML iconHTML  

    The quantitative exploration of the memory design space is needed early in the design process of deeply embedded systems. For predictive results, models are required that carefully consider three performance-impacting effects of memory accesses: synchronization, arbitration, and latency. Our approach combines functionally-correct performance simulation with memory models of different accuracy. Extending a SystemC-based framework, we leverage performance annotations to capture dynamic effects in the system. Indicative performance figures can be derived using only sparse synchronization and a statistical memory access distribution model. We observe a better predictability by 4X for our design compared to existing work. A case study demonstrates our approach exploring tradeoffs between local and shared memories in a multiprocessor SoCs using a wireless packet processing application. View full abstract»

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  • Design automation model for application-specific processors on reconfigurable fabric

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (153 KB) |  | HTML iconHTML  

    The process of embedded system design on reconfigurable architectures needs smart solutions to reduce development life-cycle and to use resources efficiently at run-time. Current solutions are insufficient to enable the embedded system designer to reflect the flexibility that a reconfigurable architecture can offer. Some of the basic problems are lack of flexible operator definitions, very detailed hardware abstraction procedures, a few or no constraints for tasks or loops at the high-level of design abstraction. In this paper, we propose a new model for automated design of application-specific processors in run-time reconfigurable architectures, solving the aforementioned inefficiency problems. Based on the proposal, a design language, a framework and a compiler have also been developed. View full abstract»

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  • Rapid prototyping of a DVB-SH turbo decoder using high-level-synthesis

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    In this paper, we present a prototyping exercise, mapping a turbo decoder high-level description directly to FPGA for fast simulation of a software radio. The turbo decoder algorithm is described in C programming language and the mapping has been done directly using the high level synthesis tool CoDeveloper. The manual transformations made on the code to facilitate efficient compilation and to achieve a tools compliant overall structure are described. The mapping exercise consists of several steps with changes resulting in improvements in performance and resource usage. The results in terms of effort of mapping and the achieved size and throughput are discussed. View full abstract»

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  • Transaction level modeling of an adaptive multi-standard and multi-application radio communication system

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (531 KB) |  | HTML iconHTML  

    Design of radio communication systems delivering wide variety of applications with the best end-user experience through the overall wireless networks implies to develop innovative services to encompass adaptation capability requirements. The creation of efficient executable models becomes a mandatory step to enable system architecting of such system under timing and power constraints. In this paper we propose a method based on the creation of an executable model at transaction level of an adaptive multi-standard and multi-application radio communication system. A specific modeling technique is proposed to represent the behavior of the system environment for different use cases. A generic model of the system is also proposed to describe several dynamic services and the reconfiguration management functionality. Simulation results provided by the model enable to study impact of reconfiguration mechanisms. View full abstract»

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  • Mixed simulation kernels for high performance virtual platforms

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (257 KB) |  | HTML iconHTML  

    We present work in the domain of Virtual Platforms, based on the QEMU emulator. Virtual Platforms allow software and drivers to be developed in parallel with the development of hardware, avoiding re-design and long delay times in SW development. This work allows designers to plug SystemC models into the virtual platforms that QEMU offers (We focused on two of the available platforms: x86 PC and ARM's VersatilePB) The new aspect of this work is the technology we have developed to connect between QEMU and SystemC. We have developed a virtual device to link QEMU and SystemC, and a bridge to manage the OSCI SystemC-2.2.0 simulator. This bridge accomplish the task of synchronize efficiency the two simulators, using a strategy of freeze-and-update on the SystemC simulator to achieve a good performance. Connection with the SystemC device is done using TLM-2.0 sockets and makes use of DMI. Also we present the same emulator wrapped for a TLM-2.0 Initiator module. With this wrapper, this QEMU module can be used in a standard SystemC simulation environment as an Initiator that accesses some (but not necessary all) of its system devices through a standard TLM-2.0 socket. View full abstract»

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  • Checkpoint and Restore for SystemC models

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (349 KB) |  | HTML iconHTML  

    We present preliminary work in the field of saving and restoring model state within a SystemC simulation environment. Save and restore (or checkpointing) is a useful technique that can greatly assist target software and simulation model development and debug. In contrast to other approaches that aim at saving and restoring the state of an entire simulation process, we investigate mechanisms by which only the essential simulation state is saved. This makes the checkpoints far more compact, and saved simulation states can be moved between host machines, and be used with updated or completely different simulation models. Our results indicate that SystemC models written to certain coding guidelines can be saved and restored reliably. As a result, virtual platforms and platform components written in SystemC can be made more useful to software developers, and support smarter workflows. View full abstract»

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  • The application of Aspectual Feature Module in the development and verification of SystemC models

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (354 KB) |  | HTML iconHTML  

    It is often the case that lots of SystemC models are needed in the development a SoC project. How to develop these models more efficiently is an urgent problem to solve. The inheritance mechanism of SystemC is not synthesizable, and its synthesizable subset is smaller than the conventional hardware description languages, which restricts the extensive use of SystemC in RTL level. Moreover, in the verification process of SystemC models, code for verification is often tangled with and scattered across the code for design, which violate the fundamental principle of software engineering: Separation of Concerns. This paper proposes for the first time to use Aspectual Feature Module (AFM) to solve the above problems. View full abstract»

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  • Another take on functional system-level design and modeling

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (265 KB) |  | HTML iconHTML  

    In this paper, we advocate a novel methodology suited for efficiently solving problems such as NoC instantiation or memory hierarchy structure determination, common in high-complexity SoCs. The proposed framework is not specific to a given NoC or memory organisation, and supports multiple and mixed abstraction levels and design paradigms. It is based on functional programming techniques such as polymorphism and monadic programming. It has been prototyped in the Haskell language. We show its usefulness on a simple example of estimation of memory accesses impact during the backprojection step of a positron emission tomography (PET) reconstruction algorithm. View full abstract»

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  • Efficient approximately-timed performance modeling for architectural exploration of MPSoCs

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (406 KB) |  | HTML iconHTML  

    In this paper, we propose an efficient modeling approach that permits simulation-based performance evaluation of MPSoCs at electronic system level (ESL). The approach is based on a SystemC simulation framework and allows for evaluating timing effects from resource contention when mapping applications to MPSoC platforms. The abstraction level used for modeling timing corresponds to approximately-timed transaction level models. This allows for an accurate performance modeling, including temporal effects from preemptive processor scheduling and bus arbitration. However, in contrast to standard SystemC TLM, application mapping and platform models are configurable and, thus, enable design space exploration at ESL. We use a motion-JPEG decoder application to illustrate and assess the benefits of the proposed approach. View full abstract»

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  • Optimizing HW/SW Co-simulation based on run-time model switching

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (333 KB)  

    The development of embedded systems nowadays is strongly supported by simulation in order to reduce development time and improve product quality. However, effects occurring e.g. on the physical level may impact the whole system and cannot be captured by using only high abstracted models. Co-simulation is a possible solution for this problem. It enables the combination of an abstracted, system level view with highly accurate models of different components, and thus supports the analysis and validation of the embedded system. In this work we present an approach based on the inter-language run-time switching of simulation models during co-simulation. This new method enables long-time system level simulation with dynamic (user defined) switches to more accurate models for the punctual analysis of low level effects. The approach is applied for the co-simulation of an automotive distributed network and enables the analysis of the system at application level with a dynamically selectable accuracy down to the signal integrity within the physical cables. View full abstract»

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  • Fast and unified SystemC AMS - HDL simulation

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (373 KB) |  | HTML iconHTML  

    An agile methodology for mixed signal simulation is presented allowing seamless connection of simulators on as needed basis eliminating overheads of the communication backplane, sophisticated synchronization and kernel modification. The methodology uses the SystemC AMS synchronization layer which supports user defined solvers and simulators. The cosimulation is wrapped in a statically scheduled timed dataflow node. The simulated executable specification enables co-design, partitioning, refinement, virtual prototyping and architecture exploration of the design space. View full abstract»

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  • A VHDL-AMS modeling methodology for top-down/bottom-up design of RF systems

    Page(s): 1 - 7
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (555 KB)  

    This paper presents a modelling methodology for the top-down/bottom-up design of RF systems based on systematic use of VHDL-AMS models. The model interfaces are parameterizable and pin-accurate. The designer can choose to parameterize the models using performance specifications or device parameters back-annotated from the transistor-level implementation. The abstraction level used for the description of the respective analog/digital component behavior has been chosen to a good trade-off between accuracy, fidelity, and simulation performance. These properties make the models suitable for different design tasks such as architectural exploration or overall system validation. This is demonstrated on a model of a binary FSK transmitter parameterized to meet very different target specifications. The achieved flexibility and systematic model documentation facilitate their reuse in other design projects. View full abstract»

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  • Design of experiments for effective pre-silicon verification of automotive electronics

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (736 KB) |  | HTML iconHTML  

    The paper presents a method to validate the compliance with value-ranged requirements of heterogeneous electronic systems with variations in a time effective way. Statistical Design of Experiments methodology is applied and adapted to plan, implement and analyze simulations of the system model, to determine key parameters that impact system performance. This is applied on a SystemC/SystemC-AMS model of an automotive Electronic Control Unit. View full abstract»

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  • A top-down approach for the design of low-power microsensor nodes for wireless sensor network

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (473 KB)  

    This paper describes the modeling of a microsensor node dedicated to wireless sensor network applications. The definition of the different node modes is first introduced: wake-up, measure, processing, transmission, reception and sleep. Then, contrary to the literature, a complete sensor node energy model is derived and used to analyze node autonomy. This model allows to estimate the part of each element of the microsensor node in its overall power consumption. Using this simple model, the impact of application specifications and element characteristics into the average power consumption can be analyzed in order to guide designer towards the best choice of components. View full abstract»

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  • HSPICE implementation of a numerically efficient model of CNT transistor

    Page(s): 1 - 5
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    This paper presents the algorithms of an implementation of a numerically efficient carbon nanotube transistor (CNT) model in HSPICE. The model is derived from cubic spline non-linear approximation of the non-equilibrium mobile charge density. The spline algorithm exploits a rapid and accurate solution of the numerical relationship between the charge density and the self-consistent voltage, which results in the acceleration of deriving the current through the channel without losing much accuracy. The output I-V characteristics of the proposed model have been compared with those of a recent HSPICE implementation of the Stanford CNT model and published experimental I-V curves. The results show superior accuracy of the proposed model while maintaining similar CPU time performance. Two versions of the HSPICE macromodel implementation have been developed and validated, one to reflect ballistic transport only and another with non-ballistic effects. To further validate the model a complementary logic inverter has also been implemented using the proposed technique and simulated in HSPICE. View full abstract»

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  • A SystemC superset for high-level synthesis

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    Today's system-on-a-chip (SoC) designs are becoming more and more complex. This creates demand for system level computer-aided-design (CAD) tools that allow early hardware and software co-development, hardware and software performance evaluation and fast system-level modeling. The latest achievements in this area are mostly due to wide SystemC adoption and the recent introduction of the TLM 2.0 standard. The complexity of today's SoC designs makes high-level synthesis (HLS) an important part of modern design flows. In this paper, we analyze two basic approaches to HLS user input that exist today sequential ANSI C/C++ and SystemC synthesizable subset. Based upon the results of our analysis, we propose a new concept SystemC synthesizable superset a solution that combines advantages of both approaches (ANSI C/C++ and SystemC), but does not inherit their disadvantages. Our HLS-oriented concept features a predefined library of HLS modules, user threads with implicit timing specification and a set of TLM 2.0 compatible interfaces. In addition, our HLS objects allow for various levels of simulation abstraction (or timing accuracy), such as cycle-accurate at transaction boundaries (CATB), approximately-timed and loosely-timed modeling. Simulation abstraction levels can be switched without the need to rewrite the user system specification that determines high flexibility level of our solution. In conclusion, we demonstrate a simple synthesizable video system and compare the simulation speeds at different abstraction levels. View full abstract»

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  • EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applications

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    In this paper, a new framework EmCodeSyn is introduced for visual debugging, execution and code synthesis from multi-rate data flow based specifications. EmCodeSyn is an attempt to create a formal semantics based visual framework for specifying safety critical applications such as automotive control, avionics fly-by-wire control, etc. In contrast with SIMULINK/Stateflow, LabVIEW and other visual tools, EmCodeSyn is based on a synchronous programming paradigm akin to the polychronous language SIGNAL. The formalism on which this work is based, is called MRICDF (multi-rate instantaneous channel connected data flow). The specification formalism has relational semantics, which enables static rate-analysis for scheduling the computation in the code generation stage. Hierarchical data flow specification with minimal amount of control specification makes it easier for designers to compose existing MRICDF models to create larger ones. Once the feasibilty of an MRICDF design is verified, code synthesis is performed by the tool to generate C code. EmCodeSyn design methodology provides a visual framework for generating verifiable deterministic code from synchronous specification based on MRICDF formalism. View full abstract»

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  • DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (287 KB) |  | HTML iconHTML  

    This paper presents a novel approach to transform DEVS models of computation into synthesizable VHDL code. By describing the transformation process thoroughly in terms of MoC timing characteristics, our approach is applicable to other discrete event based MoCs as well. The transformation engine uses rule checks to verify whether the model may be applicable to embedded real-time systems or if it may be only applicable to reduce simulation time by hardware execution. Moreover, we propose a DEVS model notation based upon state chart XML to support a superior interoperability of different tool-chains. View full abstract»

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  • Proposal to extend frequency domain analysis in VHDL-AMS

    Page(s): 1 - 4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    Small signal frequency analysis is one of the first standard methods electrical engineers are taught. Despite of its limitations it is applied to characterize and design electrical systems up to today. The actual VHDL-AMS standard supports frequency domain analysis based on linearized DAE systems. This makes it difficult to use pure frequency domain characterizations of subcircuits if, for instance, only frequency domain results are required. This paper describes a small extension of the VHDL-AMS standard that helps to overcome the problem if consistency of time and frequency domain descriptions is not required. View full abstract»

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