2009 IEEE International SOC Conference (SOCC)

9-11 Sept. 2009

Filter Results

Displaying Results 1 - 25 of 127
  • [Front cover]

    Publication Year: 2009, Page(s): c1
    Request permission for commercial reuse | |PDF file iconPDF (75 KB)
    Freely Available from IEEE
  • [Breaker pages]

    Publication Year: 2009, Page(s):1 - 5
    Request permission for commercial reuse | |PDF file iconPDF (123 KB)
    Freely Available from IEEE
  • SOCC committee

    Publication Year: 2009, Page(s): 1
    Request permission for commercial reuse | |PDF file iconPDF (54 KB)
    Freely Available from IEEE
  • 2009 Technical Program Committee

    Publication Year: 2009, Page(s): 1
    Request permission for commercial reuse | |PDF file iconPDF (78 KB)
    Freely Available from IEEE
  • List of reviewers

    Publication Year: 2009, Page(s): 1
    Request permission for commercial reuse | |PDF file iconPDF (72 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2009, Page(s):1 - 9
    Request permission for commercial reuse | |PDF file iconPDF (159 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 2009, Page(s):1 - 3
    Request permission for commercial reuse | |PDF file iconPDF (42 KB)
    Freely Available from IEEE
  • Session quick index

    Publication Year: 2009, Page(s): 1
    Request permission for commercial reuse | |PDF file iconPDF (52 KB)
    Freely Available from IEEE
  • Keynote / plenary session

    Publication Year: 2009, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (101 KB)

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Keynote speaker

    Publication Year: 2009, Page(s):3 - 4
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (163 KB) | HTML iconHTML

    While voice still makes up the majority of mobile traffic around the world, the shift in killer applications to data and multimedia is already underway. Mobile Internet is becoming the key future revenue engine, with a strong demand among business users, who want to access information anywhere and anytime, as well as in emerging markets, where customers increasingly turn to mobile phones to connec... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Plenary presentation A

    Publication Year: 2009, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (142 KB)

    With the on-going improvement of semiconductor technology, and the consequent new applications that are permitted, the complexity of SoCs continues. While technical innovations have been used to address some of the issues, there is also a reliance on putting more design engineers and more money at these SoCs to tackle this continued complexity. But are the Fabless companies really innovative? What... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Plenary presentation B

    Publication Year: 2009, Page(s): 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (173 KB)

    Due to the continue driving of the Moore's law, semiconductor technology make the tera-scale integration become possible. With so many transistors in a single chip, many dream applications become possible. Designers are eager to use those tremendous capacity of the integration circuits to bring more intelligent, more smart functions. One of the challenge target is can we design the circuits to mak... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Session WA1 FPGA design methodologies

    Publication Year: 2009, Page(s): 1
    Request permission for commercial reuse | |PDF file iconPDF (93 KB)
    Freely Available from IEEE
  • A high-level compilation toolchain for heterogeneous systems

    Publication Year: 2009, Page(s):9 - 18
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (380 KB) | HTML iconHTML

    This paper describes Harmonic, a toolchain that targets multiprocessor heterogeneous systems comprising different types of processing elements such as general-purposed processors (GPPs), digital signal processors (DSP), and field-programmable gate arrays (FPGAs) from a high-level C program. The main goal of Harmonic is to improve an application by partitioning and optimising each part of the progr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A multi-level simulation approach in a Simulink-based design tool for FPGAs

    Publication Year: 2009, Page(s):19 - 22
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (309 KB) | HTML iconHTML

    This paper describes how simulation across multi-abstraction level problem has been solved in CodeSimulink environment, a high-level design tool for FPGAs and DSPs. We detail how we achieve the desired behavior at almost every considered level (i.e., Simulink, RTL and on-chip). We also show some results on simple applications to validate the approach. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient runtime performance monitoring of FPGA-based applications

    Publication Year: 2009, Page(s):23 - 28
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (277 KB) | HTML iconHTML

    Embedded computing platforms have long incorporated non-traditional architectures (e.g., FPGAs, ASICs) to combat the diminishing returns of Moore's Law as applied to traditional processors. These specialized architectures can offer higher performance potential in a smaller space, higher power efficiency, and competitive costs. A price is paid, however, in development difficulty in determining func... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SoC framework for FPGA: A case study of LTE PUSCH receiver

    Publication Year: 2009, Page(s):29 - 32
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (178 KB) | HTML iconHTML

    An SoC framework is presented, comprising of a plug-and-play infrastructure where the system communication is abstracted from the processing elements. A software scheduler is used with a hardware modelling environment for latency analysis. Using the framework, an LTE uplink data channel (PUSCH) receiver design is shown to meet the stringent latency targets. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Session WA2 PLL and clocks

    Publication Year: 2009, Page(s): 1
    Request permission for commercial reuse | |PDF file iconPDF (93 KB)
    Freely Available from IEEE
  • Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS

    Publication Year: 2009, Page(s):35 - 38
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (338 KB) | HTML iconHTML

    Two 90 nm CMOS low power wide tuning range VCO designs are presented. A Dual Delay Ring VCO has a tuning range of 63%, consumes 6.5 mW at 6 GHz, and has a phase noise of -92d Bc/Hz at 1 MHz offset at 6 GHz center frequency. A Relaxation VCO has a tuning range of 183%, consumes 0.9 mW at 6 GHz, and has a phase noise of -83 dBc/Hz at 1 MHz offset at 6 GHz center frequency. The supply voltage is 1.2 ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator

    Publication Year: 2009, Page(s):39 - 42
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (439 KB) | HTML iconHTML

    A 5.4 GHz multiple-pass ring voltage controlled oscillator (VCO) based phase-locked loop (PLL) is described. For the sake of active devices' sensitivity to process and temperature regarding ring oscillators, an effective automatic frequency calibration scheme is proposed. A new process-independent differential to single (DTOS) is used to adjust control voltage range and loop gain. The chip is impl... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines

    Publication Year: 2009, Page(s):43 - 46
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (245 KB) | HTML iconHTML

    We propose a high-resolution 8-bit time-to-digital converter that uses two-level fractional difference conversion to reduce area and power consumption. Two delay-locked loops stabilize the propagation delay in the upper and lower buffer chains of the Vernier delay line that is used to make the measurement. In a transistor-level simulation using 0.35 ¿m technology, this architecture achieves a res... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generator

    Publication Year: 2009, Page(s):47 - 50
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (260 KB) | HTML iconHTML

    In this paper the experimental validation along with mixed system integration of a novel, modified double scroll chaotic attractor circuit, employed as a true random binary generator (TRBG) is presented. The double scroll attractor is modeled on Chua's circuit for nonlinear operation leading to double scroll chaotic behavior. The output from the chaotic circuit which is a correlated binary sequenc... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dual-band CDR using a half-rate linear phase detector

    Publication Year: 2009, Page(s):51 - 54
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (864 KB) | HTML iconHTML

    This paper describes a dual-band clock and data recovery circuit using a new half-rate linear phase detector. With the proposed sampling scheme, the phase detector produces UP/DN signals with equal pulsewidth and thus eliminates the demand of current scaling in the charge pump. The test chip fabricated by CMOS 0.18 ¿m 1P6M process can operate at 2.7 and 1.62 Gbps which satisfies the DisplayPort s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Session WA3 reconfigurable architectures

    Publication Year: 2009, Page(s): 1
    Request permission for commercial reuse | |PDF file iconPDF (114 KB)
    Freely Available from IEEE
  • A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000

    Publication Year: 2009, Page(s):57 - 60
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (203 KB) | HTML iconHTML

    In this paper, we present a novel context modeling (CM) architecture used in JPEG2000 encoder targeting next generation of cameras. The implementation is based on a newly emerging coarse-grained dynamically reconfigurable (DR) processor. A novel partial parallel architecture for the CM is introduced which can be easily tailored for the target DR processor in order to achieve higher performance res... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.