SOC Conference, 2009. SOCC 2009. IEEE International
Date 9-11 Sept. 2009
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Displaying Results 1 - 25 of 127
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[Front cover]
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PDF (75 KB)
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[Breaker pages]
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PDF (123 KB)
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SOCC committee
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PDF (54 KB)
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2009 Technical Program Committee
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PDF (78 KB)
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List of reviewers
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PDF (72 KB)
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Table of contents
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PDF (159 KB)
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Author index
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PDF (42 KB)
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Session quick index
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PDF (52 KB)
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Keynote / plenary session
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PDF (101 KB)
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Keynote speaker
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PDF (163 KB)
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Plenary presentation A
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PDF (142 KB)
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Plenary presentation B
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PDF (173 KB)
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Session WA1 FPGA design methodologies
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PDF (93 KB)
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Session WA2 PLL and clocks
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PDF (93 KB)
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A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator
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PDF (439 KB)
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A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines
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PDF (245 KB)
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Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generator
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PDF (260 KB)
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Session WA3 reconfigurable architectures
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PDF (114 KB)
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A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000
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PDF (203 KB)
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