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2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Date 7-9 Oct. 2009

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Displaying Results 1 - 25 of 68
  • [Front cover]

    Publication Year: 2009, Page(s): C1
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  • [Title page i]

    Publication Year: 2009, Page(s): i
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  • [Title page iii]

    Publication Year: 2009, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009, Page(s): iv
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  • Table of contents

    Publication Year: 2009, Page(s):v - ix
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  • Message from the Symposium Chairs

    Publication Year: 2009, Page(s):x - xi
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  • Organizing Committee

    Publication Year: 2009, Page(s): xii
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  • Program Committee

    Publication Year: 2009, Page(s): xiii
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  • In Memoriam: Professor Susumu Horiguchi

    Publication Year: 2009, Page(s):xiv - xv
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  • TTTC: Test Technology Technical Council

    Publication Year: 2009, Page(s):xvi - xviii
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  • The Future of Test -- Product Integration and its Impact on Test

    Publication Year: 2009, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (141 KB) | HTML iconHTML

    Driving leading edge products with high quality while designs, flows, and processes advance with Moore's Law will require the semiconductor industry to continue to drive for increasing innovative DFT strategies. The test industry will need to drive for new ideas in the areas of: yield analysis, modeling, test techniques, and defect / fault tolerance. To continue cost effective products while costs... View full abstract»

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  • Low DPM: Why Do We Need it and What Does it Cost!

    Publication Year: 2009, Page(s): 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB) | HTML iconHTML

    Summary form only given. Customers of semiconductor suppliers expect high quality of parts driven by the competitive market they serve. This necessary burden is on the semiconductor companies and their manufacturing locations. Few defective ICs and PCBs should get through the line to the end customers and more importantly, even fewer with reliability issues should make it to the end user. This is ... View full abstract»

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  • Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems

    Publication Year: 2009, Page(s):11 - 19
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1369 KB) | HTML iconHTML

    This paper presents a software based approach for automatic generation of digital circuitry for synthesis and incorporation in a mixed-signal circuit or system to provide built-in self-test (BIST) and measurement of the analog circuitry. The measurements supported by the BIST circuitry include frequency response (both gain and phase), linearity and noise figure. The measurements provide analog fun... View full abstract»

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  • Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points

    Publication Year: 2009, Page(s):20 - 28
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB) | HTML iconHTML

    Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving the control points. This paper investigates methods to further reduce the area overhead by replacing dedicated flip-flops which could not be replaced in [Yang ... View full abstract»

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  • Soft Core Embedded Processor Based Built-In Self-Test of FPGAs

    Publication Year: 2009, Page(s):29 - 37
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB) | HTML iconHTML

    This paper presents the first implementation of built-in self-test (BIST) of field programmable gate arrays (FPGAs) using a soft core embedded processor for reconfiguration of the FPGA resources under test, control of BIST execution, retrieval of BIST results, and fault diagnosis. The approach was implemented in Xilinx Virtex-5 FPGAs but is applicable to any FPGA that contains an internal configur... View full abstract»

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  • On-chip Generation of the Second Primary Input Vectors of Broadside Tests

    Publication Year: 2009, Page(s):38 - 46
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (315 KB) | HTML iconHTML

    Broadside tests are two-pattern scan-based tests for delay faults. One of the complications that occur in relation to the application of broadside tests from an external tester is the need to change the primary input vector applied to the circuit at-speed during the test. We explore a solution to this problem where the second primary input vector of every test is produced on chip. The important fe... View full abstract»

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  • Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience

    Publication Year: 2009, Page(s):49 - 57
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (394 KB) | HTML iconHTML

    The traditional test model of go/no-go testing being questioned by increasing delay fault manifestations has become even further challenged as a result of unpredictable soft errors. Consequent probabilistic fault manifestations shift the focus to fault resilience mechanisms and tradeoffs of false alarms vs. escapes. Fault manifestation at flip-flops necessitates solutions that rely on their harden... View full abstract»

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  • A Novel Hardened Design of a CMOS Memory Cell at 32nm

    Publication Year: 2009, Page(s):58 - 64
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (478 KB) | HTML iconHTML

    This paper proposes a new design for hardening a CMOS memory cell at the nano feature size of 32 nm. By separating the circuitry for the write and read operations, the static stability of the proposed cell configuration increases more than 4.4 times at typical process corner, respectively compared to previous designs. Simulation shows that by appropriately sizing the pull-down transistors, the pro... View full abstract»

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  • Novel High Speed Robust Latch

    Publication Year: 2009, Page(s):65 - 73
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (494 KB) | HTML iconHTML

    In this paper we propose a new robust latch, referred to as HiPeR latch. It is insensitive to TFs affecting its internal and output nodes by design (independently of the size of its transistors), thus being scalable with technology node. It presents better or comparable robustness to TFs compared to the most recent latches in literature, while providing better characteristics in terms of performan... View full abstract»

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  • Are Robust Circuits Really Robust?

    Publication Year: 2009, Page(s): 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (191 KB) | HTML iconHTML

    Nanoscale systems are characterized by increasing parameter variations as well as an increasing susceptibility to soft errors. Transient errors during system operation are no longer restricted to memories but also affect random logic, and robust circuit design has thus become a major concern for system developers. Self-checking circuits rely on redundancy to detect and compensate errors on-line. T... View full abstract»

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  • Challenges in Delay Testing of Integrated Circuits

    Publication Year: 2009, Page(s):81 - 82
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (163 KB) | HTML iconHTML

    Delay testing of integrated circuits is increasingly focused on detecting small delay defects, and improving correlation to functional test. In this talk we will describe our recent efforts and results on industrial designs. View full abstract»

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  • Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories

    Publication Year: 2009, Page(s):85 - 93
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    Hybrid CMOS/non-CMOS memories, in short hybrid memories, have been lauded as future ultra-capacity data memories. Nonetheless, such memories are going to suffer from high degree of cluster faults, which impact their reliability. This paper proposes two modified Redundant Residue Number Systems (RRNS) based error correcting codes to tolerate cluster faults in hybrid memories, namely (i) Three Non-R... View full abstract»

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  • Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power

    Publication Year: 2009, Page(s):94 - 102
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5165 KB) | HTML iconHTML

    Circuits based on magnetic logic have shown great promise as an extremely low power alternative to CMOS based circuits. However, the success or failure of such circuits hinges on the existence of a locally controllable and low power clock field. Existing work has largely assumed the availability of such a clock field that would be almost impossible to fabricate or that exhibits an ideal distributi... View full abstract»

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  • Coded DNA Self-Assembly for Error Detection/Location

    Publication Year: 2009, Page(s):103 - 111
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (382 KB) | HTML iconHTML

    This paper proposes a novel framework in which DNA self-assembly can be analyzed for error detection/ location. The proposed framework relies on coding and mapping functions that allow to establish the presence of erroneous bonded tiles based on the pattern to be assembled (as defined by the tile set) and its current aggregate. As a widely used pattern and instantiation of this process, the Sierpi... View full abstract»

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  • Errors in DNA Self-Assembly by Synthesized Tile Sets

    Publication Year: 2009, Page(s):112 - 120
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    This paper presents a study of errors that occur in DNA self-assembly using synthesized tile sets for template manufacturing. It is shown that due to the reduced size, aggregates assembled by a synthesized tile set are not error-free as those assembled by maximum-sized (referred to as a trivial tile set) as well asnon-synthesized tile sets. Compared with non-synthesized tile sets, aggregates assem... View full abstract»

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