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Dependable Computing, 2009. PRDC '09. 15th IEEE Pacific Rim International Symposium on

Date 16-18 Nov. 2009

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  • [Front cover]

    Publication Year: 2009 , Page(s): C1
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  • [Title page i]

    Publication Year: 2009 , Page(s): i
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  • [Title page iii]

    Publication Year: 2009 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009 , Page(s): iv
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  • Table of contents

    Publication Year: 2009 , Page(s): v - ix
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  • Message from the General Chair

    Publication Year: 2009 , Page(s): x
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  • Message from the Program Co-chairs

    Publication Year: 2009 , Page(s): xi
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  • Organizing Committee

    Publication Year: 2009 , Page(s): xii - xiv
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  • Program Committee

    Publication Year: 2009 , Page(s): xv - xvi
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  • list-reviewer

    Publication Year: 2009 , Page(s): xvii
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  • Reliability Analysis of Single Bus Communication with Real-Time Requirements

    Publication Year: 2009 , Page(s): 3 - 10
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (7901 KB) |  | HTML iconHTML  

    Due to continuous technology downscaling modern embedded real-time systems become more and more susceptible to the occurrence of errors. The usage of appropriate countermeasures is necessary to prevent a system failure. In this paper we present a new reliability estimation technique for such systems. As a key novelty a formal analysis method will be introduced that approximates the probability of ... View full abstract»

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  • A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding

    Publication Year: 2009 , Page(s): 11 - 16
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (292 KB) |  | HTML iconHTML  

    A new test vector compression/decompression scheme, namely a scheme of logic operation between adjacent bits (LOBAB) is presented, which is based on bitwise logic operation between itself and its previous bit. It turns all kinds of series including continuous series, such as a series of all 0s and all 1s, and reversal series, such as a series of 01 and 10, into series of all 0s by logic operation ... View full abstract»

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  • Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy

    Publication Year: 2009 , Page(s): 17 - 22
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (429 KB) |  | HTML iconHTML  

    Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration for application scheduling. In this paper, two types of variations beyond C2C are introduced, i.e., inter-pair and intra-pair variation in TLR-CMP. Intra-pair performance asymmetry c... View full abstract»

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  • Quantitative Analysis of Long-Latency Failures in System Software

    Publication Year: 2009 , Page(s): 23 - 30
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (359 KB) |  | HTML iconHTML  

    This paper presents a study on long latency failures using accelerated fault injection. The data collected from the experiments are used to analyze the significance, causes, and characteristics of long latency failures caused by soft errors in the processor and the memory. The results indicate that a non-negligible portion of soft errors in the code and data memory lead to long latency failures. T... View full abstract»

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  • A Synthesis Software Reliability Model

    Publication Year: 2009 , Page(s): 31 - 36
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (271 KB) |  | HTML iconHTML  

    In this paper, we propose a synthesis model for software reliability. For the time being, the assumptions that the architecture-based measurement makes do not address the accurate reliability of components in software, resulting in inaccuracy or even incorrectness in evaluating the software reliability. Therefore, we propose a new reliability measurement based on the software architecture, the com... View full abstract»

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  • Using the NuSMV Model Checker for Test Generation from Statecharts

    Publication Year: 2009 , Page(s): 37 - 42
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (188 KB) |  | HTML iconHTML  

    Testing is essential to ensure the dependability of software systems. This paper proposes an automatic test case generation method using the NuSMV model checker. We consider state-transition testing based on Statechart specifications. Given a Statechart specification, our proposed method can automatically generate test cases that cover all states or all transitions in the Statechart. Finding such ... View full abstract»

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  • A Novel Generation Algorithm of Pair-Wise Testing Cases

    Publication Year: 2009 , Page(s): 43 - 48
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (284 KB) |  | HTML iconHTML  

    Pair-wise testing is a practical and effective method which has already been used in the software testing. Extensive research has been made on the generation of pair-wise testing. In order to make it easy to analyze the current generation methods, we propose a method to ease the process. That is we transform the problem of pair-wise testing to a graphic one. The IPO algorithm is based on parameter... View full abstract»

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  • Impact of Hazards on Pattern Selection for Small Delay Defects

    Publication Year: 2009 , Page(s): 49 - 54
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1210 KB) |  | HTML iconHTML  

    Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test pattern selection method considering hazards. The concept of arrival time window is introduced and the concept of output deviation is redefined to accurately reflect the pattern capabi... View full abstract»

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  • Fault Injection Scheme for Embedded Systems at Machine Code Level and Verification

    Publication Year: 2009 , Page(s): 55 - 62
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (461 KB) |  | HTML iconHTML  

    In order to evaluate software from the third party whose source codes are not available, after a careful analysis of the statistic data sorted by orthogonal defect classification, and the corresponding relation between patterns of high level language programs and machine codes, we propose a fault injection scheme at machine code level suitable respectively to the IA32 ARM and MIPS architecture, wh... View full abstract»

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  • Small Delay Fault Simulation for Sequential Circuits

    Publication Year: 2009 , Page(s): 63 - 68
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (403 KB) |  | HTML iconHTML  

    Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is presented. The sizes of the faults are less than one system clock cycle. For our method, the delay distribution in the CUT is considered, and the fault size is quantized as times of the prop... View full abstract»

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  • Built-In Self-Repair Techniques for Heterogeneous Memory Cores

    Publication Year: 2009 , Page(s): 69 - 74
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (460 KB) |  | HTML iconHTML  

    In this paper, BISR (built-in self-repair) techniques for heterogeneous multiple memory cores with divided redundancy mechanism are proposed. Redundant memories are partitioned into row blocks and column blocks and shared among all memory cores in the same memory group. Therefore, unlike the traditional redundancy mechanism, a row (column) block is used as the basic replacement element. Based on t... View full abstract»

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  • Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan

    Publication Year: 2009 , Page(s): 75 - 80
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1292 KB) |  | HTML iconHTML  

    Enhanced scan delay testing approach can achieve high transition delay fault coverage by a small size of test pattern set but with significant hardware overhead. Although the implementation cost of launch on capture (LOC) approach is relatively low, the generated pattern set for testing delay faults is typically very large. In this paper, we present a novel flip-flop selection method to combine th... View full abstract»

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  • A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing

    Publication Year: 2009 , Page(s): 81 - 86
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (191 KB) |  | HTML iconHTML  

    Power-aware X-filling is a preferable approach to avoiding IR-drop-induced yield loss in at-speed scan testing. However, the quality of previous X-filling methods for reducing launch switching activity may be unsatisfactory, due to low effect (insufficient and global-only reduction) and/or low scalability (long CPU time). This paper addresses this quality problem with a novel, GA (Genetic Algorith... View full abstract»

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  • On the Computational Complexity of Parameter Estimation in Adaptive Testing Strategies

    Publication Year: 2009 , Page(s): 87 - 92
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    Adaptive testing is the counterpart of adaptive control in software testing. It means that software testing strategy should be adjusted on-line by using the testing data collected during software testing as our understanding of the software under test improves. In doing so, online estimation of parameters plays a crucial role. In this paper, we investigate the computational complexity of the param... View full abstract»

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  • A New Approach to Automated Redundancy Reduction for Test Sequences

    Publication Year: 2009 , Page(s): 93 - 98
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    The problem of redundancy among test sequences derived from different FSM-based test coverage criteria often emerges in practice, resulting in the increasing of test cost of software. To solve this problem, a novel approach by way of string matching to eliminating redundancy among test sequences is presented in the paper. Four types of redundancies of test sequences are described and the correspon... View full abstract»

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