Date 9-11 Dec. 2009
Filter Results
Displaying Results 1 - 25 of 100
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[Front cover]
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PDF (1852 KB)
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[Title page]
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PDF (244 KB)
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Message from the general chair and program co-chairs
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PDF (24 KB)
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Organizing Committee
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PDF (44 KB)
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Implementation of a foveal vision mapping
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PDF (308 KB)
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An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher
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PDF (742 KB)
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Towards a balanced ternary FPGA
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PDF (751 KB)
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Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design
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PDF (203 KB)
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VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems
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PDF (392 KB)
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PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess
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PDF (290 KB)
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A detailed delay path model for FPGAs
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PDF (834 KB)
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Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells
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PDF (402 KB)
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