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Date 23-26 Nov. 2009

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Displaying Results 1 - 25 of 92
  • [Front cover]

    Publication Year: 2009, Page(s): C1
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  • [Title page i]

    Publication Year: 2009, Page(s): i
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  • [Title page iii]

    Publication Year: 2009, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009, Page(s): iv
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  • Table of contents

    Publication Year: 2009, Page(s):v - xi
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  • Foreword

    Publication Year: 2009, Page(s): xii
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  • Organizing Committee

    Publication Year: 2009, Page(s): xiii
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  • Steering Committee

    Publication Year: 2009, Page(s): xiv
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  • Program Committee

    Publication Year: 2009, Page(s):xv - xvi
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  • list-reviewer

    Publication Year: 2009, Page(s): xvii
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  • Tutorials

    Publication Year: 2009, Page(s):xviii - xix
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Keynotes

    Publication Year: 2009, Page(s):xx - xxiii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (162 KB)

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Best Paper Award of ATS 2008

    Publication Year: 2009, Page(s): xxiv
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  • Call for Papers of ATS 2010

    Publication Year: 2009, Page(s): xxv
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  • CA Based Built-In Self-Test Structure for SoC

    Publication Year: 2009, Page(s):3 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (349 KB) | HTML iconHTML

    This paper reports synthesis of a built-in self-test logic for the cores integrated into an SoC. The test logic is developed around a nonlinear cellular automata (CA). The CA based scalable PRPG, synthesized in linear time (O(n)), enables the design of such a highly efficient test logic. The cascadable structure of the PRPG is utilized to construct the on-chip Test Pattern Generators (TPGs) for th... View full abstract»

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  • A Random Jitter RMS Estimation Technique for BIST Applications

    Publication Year: 2009, Page(s):9 - 14
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (367 KB) | HTML iconHTML

    This paper describes a RMS value measurement technique for random jitter. A jittery clock signal is combined with a reference clock signal using an OR operation and an AND operation in sequence, and the pulse width outputs modulated by the amount of the random jitter are used to charge or discharge a capacitor. The voltage at the capacitor, in turn, modulates the frequency of VCO having a current-... View full abstract»

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  • A Novel Seed Selection Algorithm for Test Time Reduction in BIST

    Publication Year: 2009, Page(s):15 - 20
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    The seed (initial state) of a pseudo-random pattern generator (PRPG) for built-in self-test (BIST), significantly influences the fault coverage and total test application time. This paper introduces a one-pass seed selection algorithm, for any known PRPG. Due to its single-pass nature, unlike the state-of-the-art exhaustive search methods, the proposed algorithm is more time and memory efficient. ... View full abstract»

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  • Logic BIST Architecture for System-Level Test and Diagnosis

    Publication Year: 2009, Page(s):21 - 26
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (321 KB) | HTML iconHTML

    This paper describes the logic built-in self-test (BIST) architecture for test and diagnosis of ASIC devices at the system level. The proposed architecture supports the at-speed staggered launch-on-capture clocking scheme and includes novel features to further increase the device's defect coverage, place-and-route ability, ease of debug and diagnosis, and reduce test power consumption. These featu... View full abstract»

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  • Fault Diagnosis under Transparent-Scan

    Publication Year: 2009, Page(s):29 - 34
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (266 KB) | HTML iconHTML

    Transparent-scan provides opportunities for test compaction that do not exist with the conventional test application scheme for scan circuits. However, test compaction can reduce the ability of a transparent-scan sequence to diagnose faults. We describe a static test compaction procedure that reduces the length of a transparent-scan sequence while maintaining its stuck-at fault coverage and the nu... View full abstract»

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  • Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns

    Publication Year: 2009, Page(s):35 - 40
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (754 KB) | HTML iconHTML

    In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper we first analyze the advantages and disadvantages of each category of the chain diagnosis algorithms. Next, an adaptive signal profiling algorithm that can use manufacturing ATPG scan patterns is proposed for scan chain diag... View full abstract»

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  • On Improving Diagnostic Test Generation for Scan Chain Failures

    Publication Year: 2009, Page(s):41 - 46
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (434 KB) | HTML iconHTML

    In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-cycle scan test patterns. A diagnostic test generation flow to speed up diagnosis is proposed to address the issue of long run times of test generation and large number of test patterns for the cases where the range of su... View full abstract»

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  • On Scan Chain Diagnosis for Intermittent Faults

    Publication Year: 2009, Page(s):47 - 54
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB) | HTML iconHTML

    Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper,... View full abstract»

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  • Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique

    Publication Year: 2009, Page(s):57 - 62
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB) | HTML iconHTML

    In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would c... View full abstract»

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  • Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients

    Publication Year: 2009, Page(s):63 - 68
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (338 KB) | HTML iconHTML

    A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of th... View full abstract»

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  • Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs

    Publication Year: 2009, Page(s):69 - 74
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2112 KB) | HTML iconHTML

    In this paper, a low-cost test methodology for dynamic specifications of high precision sigma-delta (ΔΣ) analog-to-digital converters (ADCs) is presented. Dynamic testing of ADCs requires an input test stimulus with total harmonic distortion (THD) and signal-to-noise ratio (SNR) about 10 dB better than the ADC under test. ΔΣ ADCs are inherently high resolution conve... View full abstract»

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