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Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211)

2-3 Feb. 1998

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  • Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211)

    Publication Year: 1998
    Request permission for commercial reuse | PDF file iconPDF (250 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1998, Page(s): 149
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    Freely Available from IEEE
  • Trends in BGA design methodologies

    Publication Year: 1998, Page(s):120 - 123
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (24 KB)

    Ball grid array packaging has emerged as the technology of choice for high I/O count ICs, delivering high density and yield without requiring fine-pitch processing or new assembly equipment. Many similarities exist between these advanced packages and traditional printed circuit boards, but the design process is not one of them. Incorporating one or several complex ICs into a BGA package is dramati... View full abstract»

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  • Shorting via arrays for the elimination of package resonance to reduce power supply noise in multi-layered area-array IC packages

    Publication Year: 1998, Page(s):116 - 119
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    This paper presents full-wave electromagnetic field simulations on the effects of shorting via arrays for the reduction of power and ground noise in IC packages. Properties of internal resonance in multilayered packages are studied. Effects of area-array power and ground vias of different densities are evaluated by examining the input impedances of the package power supply. It is shown that, by pr... View full abstract»

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  • Lossy substrate and resonance analysis of embedded inductors

    Publication Year: 1998, Page(s):109 - 114
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Integrated spiral inductors, while practically desirable and technologically feasible, challenge the modeling efforts by their half-distributed and half-lumped nature and substrate loss at high frequencies. In this paper, we examine these effects by full-wave solving. Full-wave Green's functions are developed, which capture the substrate coupling and loss effects. It is shown that the substrate lo... View full abstract»

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  • A step towards MCM design automation

    Publication Year: 1998, Page(s):74 - 80
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    The implementation of complex electronic systems using high density packaging (HDP) technologies requires an IC-like “right first-time” design approach, as rework and prototyping for such technologies can be extremely expensive. On the other hand, most multichip module (MCM) and HDP technologies have not yet reached a mature stage. Highly integrated and versatile MCM design environment... View full abstract»

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  • Modeling requirements and techniques for plastic packages used in RFICs

    Publication Year: 1998, Page(s):105 - 108
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    Successful RFIC designs in low cost plastic packages requires special design considerations to be applied in the areas of package selection and management of the parasitics the package introduces. Accurate modeling and characterization of the package is also a key ingredient in being successful in RFIC design. This paper describes the design considerations, modeling and verification processes used... View full abstract»

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  • EDA tools for high-performance MCM

    Publication Year: 1998, Page(s):70 - 73
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    High density interconnect and MCM designs involve a variety of diverse technologies, including ceramics, laminates and deposited thin films as well as combinations of technologies such as hybrid MCM-D/L. Chips may be attached in CSP (chip scale packages) or via flip chip or bonded techniques. A design tool suite that encompasses all these substrate technologies, packages, chip packages and attache... View full abstract»

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  • Seamless high off-chip connectivity [IC packaging]

    Publication Year: 1998, Page(s):39 - 44
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Seamless high off-chip connectivity (SHOCC) is a combined packaging, interconnect, and IC design philosophy based on a wire hierarchy distributed between the active die and a passive interconnection substrate. SHOCC takes a system level view of the chip, package and substrate requirements to shift the device fabrication paradigm from the current single die approach to a parallel manufacturing sche... View full abstract»

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  • System technology challenges facing the PC industry

    Publication Year: 1998
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8 KB)

    Personal computers (PCs) currently exhibit performance levels comparable to those of mainframe computers only a few years ago. Trends also suggest a sustained 2× yearly increase in performance per unit cost. These improvements are coupled with marked increases in heat dissipation and electromagnetic emissions with tighter requirements for power delivery and high speed signalling. In contrast... View full abstract»

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  • Error estimation of reduced-order modeling of high speed RLCG circuit

    Publication Year: 1998, Page(s):143 - 148
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    In this paper, we show that perturbations in pole valves in reduced-order modeling of RLCG circuits play a crucial role in the accuracy of time-domain simulation. We first derive a simple formula that expresses the error accumulation in the time domain as a function of the simulation time and perturbation of the pole values. Then, a posteriori error bound estimation of the poles generated by any m... View full abstract»

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  • MCM-D implementation of passive RF components: Chip/package tradeoffs

    Publication Year: 1998, Page(s):100 - 104
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    MCM-D technology offers the capability to integrate passive components with ICs. Currently, most application volume is in a frequency range between 800 MHz and 2 GHz. On-chip integration of inductors in this range poses particular problems because of the conflicting needs for small size and high quality factor. MCM technology offers a way to tightly integrate inductors and capacitors in a more cos... View full abstract»

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  • Early analysis of chip scale package design trade-offs

    Publication Year: 1998, Page(s):64 - 69
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Chip scale packages (CSPs) present new challenges for both package designer and package user. It is possible to make package design trade-offs between package size, I/O pattern, thermal/electrical performance and cost for a given IC. An ideal set of CSP design trade-offs for one application may be a poor selection for another. Early analysis tools give technical information needed to select and de... View full abstract»

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  • Long lossy lines (L3) and their impact upon large chip performance

    Publication Year: 1998, Page(s):28 - 38
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    The semiconductor industry expects the performance of microprocessors to continue at its current rate of improvement, i.e. clock rates should double every two to three years. This is a commendable goal, but it is also fair to question whether this is an achievable goal. The fundamental problem is that as ground rules are reduced, the natural tendency is to make smaller conductor cross-sectional ar... View full abstract»

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  • Parasitic characteristics of BGA packages

    Publication Year: 1998, Page(s):124 - 129
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    With the rapid progress in CMOS VLSI technology, feature size has decreased dramatically from 0.5 to 0.25 μm, while chip drivers have become faster with sub-ns transitions. Most modern ICs work with a low power supply voltage with a low logic swing, and have widened their data bus from 16 to 32 or even 64 bits. All of these factors push modern packages toward greater pin counts, smaller form fa... View full abstract»

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  • Improving microprocessor performance with flip chip package designs

    Publication Year: 1998, Page(s):82 - 87
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (60 KB)

    This paper describes the extent to which flip chip packaging is advantageous in comparison to the wire bond method on otherwise comparable chips. We discuss both the engineering reasons as to why flip chip packages should be faster and the statistical method used to verify the engineering conclusions with planned experimental data about actual microprocessors. Electrical modeling predicted that th... View full abstract»

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  • Scaling and performance implications for power supply and other signal routing constraints imposed by I/O pad limitations

    Publication Year: 1998, Page(s):45 - 50
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    More than ever, accurate, high-frequency operation of integrated circuits, with smaller devices buried under an expanding superstructure of interconnect layers, depends upon advancements in packaging interface technology. Specifically, we project that at the 50 nm technology node, upwards of 4000 pads/cm2 will be required to attain acceptable on-chip power supply uniformity to assure ad... View full abstract»

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  • Embedded memories in a 32 bit high performance microcontroller

    Publication Year: 1998, Page(s):4 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    In recent years, there has been a constant demand for higher package pin counts due to higher chip complexity offered by increasingly sophisticated semiconductor technology. Microprocessors and telecommunication chips were some of the most active driving forces. This paper describes the exact opposite: approaches from the design side to tackle the pin count problem to actually reduce the demand on... View full abstract»

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  • Order reduction of high-speed interconnect electrical models: The issue of passivity

    Publication Year: 1998, Page(s):132 - 137
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    Rapid distributed circuit simulation is now being recognized as a critical component of next-generation computer-aided design frameworks to be used for performance evaluation and design of the information processing and communication systems of the 21st century. Apart from very simple systems, computer simulation of electromagnetic interactions in high-speed interconnects and packaging structures ... View full abstract»

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  • Issues in chip-package codesign with MCM-D/flip-chip technology

    Publication Year: 1998, Page(s):88 - 92
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    By distributing on-chip global power, ground, and clock planes on a thin film MCM, the IC can be made smaller, faster, and less noisy while consuming less power. These advantages are demonstrated by a number of case studies: two demonstrator ICs and an analysis of the DEC Alpha 21264 clock distribution scheme. However, there are a number of practical issues that need to be addressed, including pro... View full abstract»

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  • Output buffer with self-adjusting slew rate and on-chip compensation

    Publication Year: 1998, Page(s):51 - 55
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    In this paper, two circuits are proposed to effectively control IC noise. The first circuit is a modified I/O circuit that monitors the local output switching condition, and intelligently adjusts its slew rate such that the I/O can switch as fast as it is allowed without jeopardizing noise performance. The second circuit is a PVT-compensation control circuit, which senses process, voltage, and tem... View full abstract»

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  • Design considerations and packaging of a Pentium(R) Pro Processor based multi-chip module for high performance workstation and servers

    Publication Year: 1998, Page(s):9 - 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB)

    This paper discusses the design strategies and trade-offs considered for the design and implementation of a 1 Mbyte second level cache version of Intel's Pentium(R) Pro Processor. This document covers the design goals, packaging, and MCM routing, as well as discussion of simulation vs. measured results with regard to electrical and thermal aspects of the design View full abstract»

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  • Vector compaction for efficient simulation-based power estimation [CMOS design]

    Publication Year: 1998, Page(s):138 - 142
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    Low power digital CMOS circuit design requires accurate power estimation. To achieve the accuracy of dynamic power estimation and the speed of static estimation methods, one approach is to generate a compact, representative vector set with similar switching behaviour to the original larger vector set. In this paper, we present an algorithm based on fractal concepts to generate a compacted vector t... View full abstract»

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  • Implications of area-array I/O for row-based placement methodology

    Publication Year: 1998, Page(s):93 - 98
    Cited by:  Papers (11)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    We empirically study the implications of area-array I/O for placement methodology. Our work develops a three-axis testbed that examines (1) I/O pad regime (area-array vs. peripheral pad locations), (2) I/O and core placement methodology (variants of alternating vs. simultaneous I/O and core placement approaches), and (3) placement engine (hierarchical quadratic for both core and I/O cells vs. pure... View full abstract»

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  • Understanding models of substrate behaviour for the routing of high I/O packages

    Publication Year: 1998, Page(s):58 - 63
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    This paper explores two models of substrate wireability and examines the implications of these models in the forecast of the application of future generation integrated circuits and their packages, especially emerging generations of chip scale packages (CSPs). This is in order to clarify our understanding of potential technology bottlenecks. This analysis shows how the demands of future generation... View full abstract»

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