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1-6 Nov. 2009

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Displaying Results 1 - 25 of 119
  • [Front cover]

    Publication Year: 2009, Page(s): c1
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  • [Title page]

    Publication Year: 2009, Page(s): i
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  • [Copyright notice]

    Publication Year: 2009, Page(s): ii
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  • Table of contents

    Publication Year: 2009, Page(s):iii - xi
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  • Welcome message

    Publication Year: 2009, Page(s): 1
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  • Steering committee and subcommittees

    Publication Year: 2009, Page(s):2 - 3
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  • ITC 2008 paper awards

    Publication Year: 2009, Page(s): 4
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  • ITC 2009 most significant paper award

    Publication Year: 2009, Page(s): 5
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  • Technical Program Committee

    Publication Year: 2009, Page(s):6 - 10
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  • ITC technical paper evaluation and selection process

    Publication Year: 2009, Page(s): 11
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  • Keynote address

    Publication Year: 2009, Page(s): 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB) | HTML iconHTML

    The author describes how design, manufacturing, and test can join forces, and collaborate to battle the nanometer challenges in the semiconductor industry. View full abstract»

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  • Invited address

    Publication Year: 2009, Page(s): 13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (475 KB) | HTML iconHTML

    Summary form only given. Compute performance increased by orders of magnitude in the last few decades, made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize novel architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill continues to ful... View full abstract»

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  • TTTC: Test Technology Technical Council

    Publication Year: 2009, Page(s):14 - 16
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  • 2009 technical paper reviewers

    Publication Year: 2009, Page(s):17 - 22
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  • Author index

    Publication Year: 2009, Page(s):1 - 2
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  • Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study

    Publication Year: 2009, Page(s):1 - 10
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    Shrinking feature size and increased wire density increase the likelihood of occurrence of bridge related defects. N- detect based pattern sets are used commonly to improve the detection of bridge defects. However, achieving high bridge coverage requires deterministic bridge sites extraction from physical layout and bridge fault pattern generation. In this paper, we present a comprehensive compara... View full abstract»

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  • Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs

    Publication Year: 2009, Page(s):1 - 10
    Cited by:  Papers (22)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (457 KB) | HTML iconHTML

    Industry is facing increasingly tougher quality requirements for more complex ICs. To meet these quality requirements we need to improve the defect coverage. This paper presents a new methodology to significantly increase the defect coverage of the test patterns generated by ATPG tools. The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults. In contrast ... View full abstract»

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  • Test effectiveness evaluation through analysis of readily-available tester data

    Publication Year: 2009, Page(s):1 - 10
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1117 KB) | HTML iconHTML

    Test metrics and fault models continue to evolve to keep up with defect characteristics associated with ever-changing fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is therefore important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. Test-metric and fault model evaluation traditionally ... View full abstract»

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  • Application of non-parametric statistics of the parametric response for defect diagnosis

    Publication Year: 2009, Page(s):1 - 10
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (193 KB) | HTML iconHTML

    This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified on the 130nm ASIC. Good die responses are correlated for same parametric tests at different conditions such as temperature, voltage and or other stress. Nonparametric correlation methods ... View full abstract»

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  • Testing bridges to nowhere - combining Boundary Scan and capacitive sensing

    Publication Year: 2009, Page(s):1 - 10
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB) | HTML iconHTML

    As printed circuit board dimensions continue to decrease, in-circuit tester (ICT) access using a bed-of-nails plus capacitive sensing is increasingly difficult. Stimulus injection using IEEE 1149.1 boundary-scan has been proposed as an alternative, but without modification it has significant limitations. An IEEE-supported Working Group is developing an extension entitled, ¿1149.8.1 - Draft standa... View full abstract»

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  • Intel® IBIST, the full vision realized

    Publication Year: 2009, Page(s):1 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3318 KB) | HTML iconHTML

    Third generation Intel®IBIST (IBIST) is the first full featured edition of what was originally envisioned in 1999. The objective was to create a standard infrastructure for validating, debugging, and testing high speed IOs (Input/Output) which could be supported by a common software toolset. This vision was realized in 2009 on Intel products. The IBIST methodology has become a standard... View full abstract»

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  • Fast extended test access via JTAG and FPGAs

    Publication Year: 2009, Page(s):1 - 7
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (227 KB) | HTML iconHTML

    This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard boundary scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our soluti... View full abstract»

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  • Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry

    Publication Year: 2009, Page(s):1 - 10
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (589 KB) | HTML iconHTML

    Increasing circuit densities and speeds are quickly reducing electrical test point access for printed circuit assembly test. Boundary-scan (JTAG/IEEE 1149.x) is a technology that will allow continued testability of printed circuit assemblies, but its use requires that it be designed into semiconductor devices. Currently, not all semiconductor suppliers support boundary-scan. Wider availability of ... View full abstract»

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  • Minimizing outlier delay test cost in the presence of systematic variability

    Publication Year: 2009, Page(s):1 - 10
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1899 KB) | HTML iconHTML

    This work proposes a methodology to minimize the application cost of outlier analysis when applied to delay testing in the presence of systematic variability. Support vector machine (SVM) outlier analysis algorithms and traditional entropy measures are used to detect delay defects by choosing a minimum number of suitable test clocks. Monte Carlo simulations generate realistic test data while infor... View full abstract»

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  • Accurate measurement of small delay defect coverage of test patterns

    Publication Year: 2009, Page(s):1 - 10
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    Small delay defect (SDD) testing is expected to become more prevalent as technology nodes continue to shrink and design frequencies continue to increase. In this paper, we critically examine previously published methods for evaluating SDD coverage and identify their shortcomings as an accurate and practical coverage metric. We propose an accurate method for measuring the coverage of small delay de... View full abstract»

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