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2009 Formal Methods in Computer-Aided Design

15-18 Nov. 2009

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  • [Front cover]

    Publication Year: 2009, Page(s): c1
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  • [Title page]

    Publication Year: 2009, Page(s): i
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  • [Copyright notice]

    Publication Year: 2009, Page(s): ii
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  • Table of contents

    Publication Year: 2009, Page(s):iii - iv
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  • Preface

    Publication Year: 2009, Page(s):v - vi
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  • FMCAD 2009 conference organization

    Publication Year: 2009, Page(s):vii - ix
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  • Keynotes

    Publication Year: 2009, Page(s):x - xi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (111 KB)

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Tutorials

    Publication Year: 2009, Page(s):xii - xiii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (109 KB)

    Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Industrial

    Publication Year: 2009, Page(s):xiv - xvi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (138 KB)

    Summary form only given. In this talk, I will introduce the formal verification challenges encountered in the design of Anton, a massively parallel, special-purpose machine for molecular dynamics simulations. I will review approaches that have had the most impact on the design verification of the chip, such as bug hunting, root-cause analysis, coverage closure and deadlock detection. A particular ... View full abstract»

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  • Panels

    Publication Year: 2009, Page(s):xvii - xviii
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  • Interpolation-sequence based model checking

    Publication Year: 2009, Page(s):1 - 8
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB) | HTML iconHTML

    SAT-based model checking is the most widely used method for verifying industrial designs against their specification. This is due to its ability to handle designs with thousands of state elements and more. The main drawback of using SAT-based model checking is its orientation towards ¿bug-hunting¿ rather than full verification of a given specification. Previous works demonstrated how Unbounded M... View full abstract»

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  • Structure-aware computation of predicate abstraction

    Publication Year: 2009, Page(s):9 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB) | HTML iconHTML

    The precise computation of abstractions is a bottleneck in many approaches to CEGAR-based verification. In this paper, we propose a novel approach, based on the use of structural information. Rather than computing the abstraction as a single, monolithic quantification, we provide a structure-aware abstraction algorithm, based on two complementary steps. The first, highlevel step exploits the struc... View full abstract»

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  • Enhanced verification by temporal decomposition

    Publication Year: 2009, Page(s):17 - 24
    Cited by:  Papers (2)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    This paper addresses the presence of logic which has relevance only during initial time frames in a hardware design. We examine transient logic in the form of signals which settle to deterministic constants after some prefix number of time frames, as well as primary inputs used to enumerate complex initial states which thereafter become irrelevant. Experience shows that a large percentage of hardw... View full abstract»

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  • Software model checking via large-block encoding

    Publication Year: 2009, Page(s):25 - 32
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (231 KB) | HTML iconHTML

    Several successful approaches to software verification are based on the construction and analysis of an abstract reachability tree (ART). The ART represents unwindings of the control-flow graph of the program. Traditionally, a transition of the ART represents a single block of the program, and therefore, we call this approach single-block encoding (SBE). SBE may result in a huge number of program ... View full abstract»

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  • Verification of recursive methods on tree-like data structures

    Publication Year: 2009, Page(s):33 - 40
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB) | HTML iconHTML

    Programs that manipulate heap-allocated data structures present a formidable challenge for algorithmic verification. Recursive procedures (methods) in such software libraries are used for a large number of tasks ranging from simple traversals to complex structural transformations. Verification of such methods is undecidable in general. Hence, we present a programming language fragment with a synta... View full abstract»

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  • MCC: A runtime verification tool for MCAPI user applications

    Publication Year: 2009, Page(s):41 - 44
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB) | HTML iconHTML

    We present a dynamic verification tool MCC for Multicore Communication API applications - a new API for communication among cores. MCC systematically explores all relevant interleavings of an MCAPI application using a tailor-made dynamic partial order reduction algorithm (DPOR). Our contributions are (i) a way to model the non-overtaking message matching relation underlying MCAPI calls with a high... View full abstract»

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  • Generalized, efficient array decision procedures

    Publication Year: 2009, Page(s):45 - 52
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (342 KB) | HTML iconHTML

    The theory of arrays is ubiquitous in the context of software and hardware verification and symbolic analysis. The basic array theory was introduced by McCarthy and allows to symbolically representing array updates. In this paper we present combinatory array logic, CAL, using a small, but powerful core of combinators, and reduce it to the theory of uninterpreted functions. CAL allows expressing pr... View full abstract»

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  • Decision diagrams for linear arithmetic

    Publication Year: 2009, Page(s):53 - 60
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (537 KB) | HTML iconHTML

    Boolean manipulation and existential quantification of numeric variables from linear arithmetic (LA) formulas is at the core of many program analysis and software model checking techniques (e.g., predicate abstraction). We present a new data structure, Linear Decision Diagrams (LDDs), to represent formulas in LA and its fragments, which has certain properties that make it efficient for such tasks.... View full abstract»

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  • Efficient decision procedure for non-linear arithmetic constraints using CORDIC

    Publication Year: 2009, Page(s):61 - 68
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (239 KB) | HTML iconHTML

    In verification of hybrid discrete-continuous and embedded control systems, one encounters decision problems involving non-linear constraints. We propose an efficient decision procedure (CORD) for such decisions problems using CORDIC algorithms, and an off-the-shelf SMT(LA) (Satisfiability Modulo Theory for Linear Arithmetic) solver, for given precision requirements. We first translate the non-lin... View full abstract»

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  • Mixed abstractions for floating-point arithmetic

    Publication Year: 2009, Page(s):69 - 76
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (167 KB) | HTML iconHTML

    Floating-point arithmetic is essential for many embedded and safety-critical systems, such as in the avionics industry. Inaccuracies in floating-point calculations can cause subtle changes of the control flow, potentially leading to disastrous errors. In this paper, we present a simple and general, yet powerful framework for building abstractions from formulas, and instantiate this framework to a ... View full abstract»

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  • Safety first: A two-stage algorithm for LTL games

    Publication Year: 2009, Page(s):77 - 84
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (225 KB) | HTML iconHTML

    In the game theoretic approach to the synthesis of reactive systems, specifications are often given as a conjunction of linear time properties. An implementation can be obtained from a winning strategy derived from a suitable generalized parity game in which each property produces a parity acceptance condition. Safety and persistence properties usually make up the majority of the specification. We... View full abstract»

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  • Synthesizing robust systems

    Publication Year: 2009, Page(s):85 - 92
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (199 KB) | HTML iconHTML

    Many specifications include assumptions on the environment. If the environment satisfies the assumptions then a correct system reacts as intended. However, when the environment deviates from its expected behavior, a correct system can behave arbitrarily. We want to synthesize robust systems that degrade gracefully, i.e., a small number of environment failures should induce a small number of system... View full abstract»

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  • Formal verification of analog designs using MetiTarski

    Publication Year: 2009, Page(s):93 - 100
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (163 KB) | HTML iconHTML

    MetiTarski, an automatic theorem prover for inequalities on real-valued elementary functions, can be used to verify properties of analog circuits. First, a closed form solution to the model of the circuit is obtained. We present two techniques for obtaining the closed form solution. One is based on piecewise linear modeling and the inverse Laplace transform. The other is based on small-signal anal... View full abstract»

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  • Formal verification of correctness and performance of random priority-based arbiters

    Publication Year: 2009, Page(s):101 - 107
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (129 KB) | HTML iconHTML

    Arbiters play a critical role in the performance of electronic systems. In this paper, we describe a novel method to formally verify correctness and performance of random priority-based arbiters. We define a property of random number sequences, called Complete Random Sequence (CRS), to characterize bounded fairness properties of random number generators and random priority-based arbiters. We propo... View full abstract»

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  • Assume-guarantee validation for STE properties within an SVA environment

    Publication Year: 2009, Page(s):108 - 115
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (218 KB) | HTML iconHTML

    Symbolic Trajectory Evaluation is an industrial-strength verification method, based on symbolic simulation and abstraction, that has been highly successful in data path verification, especially microprocessor execution units. These correctness results are typically obtained under certain assumptions about how the verified hardware block's inputs are driven, as well as assumptions about the values ... View full abstract»

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